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CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 1 of 252 true system-on-chip with low powe r rf transceiver and 8051 mcu applications ? wireless keyboard and mouse ? wireless voice-quality audio ? cc2511fx: usb dongles ? remote controls ? wireless sports and leisure equipment ? point-of-sale systems ? active rfid and asse t tracking systems ? home and building automation ? low power telemetry ? 2.4 ghz ism/srd band systems product description the CC2510FX/cc2511fx is a low-cost true system-on-chip (soc) device designed for low- power and low-voltage wireless communication applications. the CC2510FX/cc2511fx combines the excellent performance of the state-of-the-art rf transceiver cc2500 with an industry-standard enhanced 8051 mcu, 8/16/32 kb of in-system programmable flash memory, 1/2/4 kb of ram and many other powerful features. the CC2510FX/cc2511fx is available in six different versions: cc2510f8 and cc2511f8 with 8 kb of flash and 1 kb of ram, the cc2510f16 and cc2511f16 with 16 kb of flash and 2 kb of ram, and cc2510f32 and cc2511f32 with 32 kb of flash and 4 kb of ram. the CC2510FX/cc2511fx is highly suited for systems where very low power consumption is required. this is ensured by several advanced low-power operating modes. the cc2511fx adds a full-speed usb interface to the feature set of the CC2510FX . interfacing to a pc using the usb interface is quick and easy, and the high data rate (12 mbps) of the usb interface avoids the bottlenecks of rs- 232 or low-speed usb interfaces. reset_n p2_4 p2_3 p2_2 p2_1 p2_0 p1_4 p1_3 p1_2 p1_1 p1_0 p1_7 p1_6 p1_5 p0_4 p0_3 p0_2 p0_1 p0_0 dp dm p0_5 rf_p rf_n xosc_q2 xosc_q1 vdd (2.0 - 3.6 v) dcoupl digital analog mixed p0_7 p0_6 key features ? high performance and low power 8051 microcontroller core. ? high-performance cc2500 rf transceiver based on the market-leading cc2500 ? frequency band: 2.4 ghz ? 8/16/32 kb in-system programmable flash ? 1/2/4 kb ram + 1 kb usb fifo ( cc2511fx ) ? full-speed usb controller ( cc2511fx ) ? i2s interface ? 8-14 bits adc with up to eight inputs ? 128-bit aes security coprocessor ? powerful dma functionality ? two usarts ? 16-bit timer with configurable ? mode ? three 8-bit timers ? hardware debug support ? 21 ( CC2510FX ), 19 ( cc2511fx ) gpio pins ? wide supply voltage range (2.0v ? 3.6v) ? high sensitivity (?100 dbm at 10 kbps) ? programmable data rate up to 500 kbps ? low current consumption (rx: 22 ma, tx: 23 ma, with mcu running at 26 mhz) ? mcu current consumption 270 a/mhz ? programmable output power up to 1 dbm for all supported frequencies ? digital rssi / lqi support ? excellent receiver selectivity and blocking performance ? 0.3 a consumption in lowest power mode ? rohs compliant 6x6mm qlp36 package this data sheet contains preliminary data, and supplem entary data will be published at a later date. chipcon reserves the right to make changes at any time with out notice in order to improve design and supply the best possible product. the product is not yet fully qualified at this point .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 2 of 252 table of contents 1 abbreviations.................................................................................................................. ...5 2 references ..................................................................................................................... ......6 3 register conventions...................................................................................................6 4 features (continued from front page).............................................................8 4.1 h igh -p erformance and l ow -p ower 8051-c ompatible m icrocontroller .......................8 4.2 8/16/32 k b n on - volatile p rogram m emory and 1/2/4 k b d ata m emory ..........................8 4.3 f ull -s peed usb c ontroller ( cc2511f x ) ................................................................................8 4.4 i2s i nterface ..............................................................................................................................8 4.5 h ardware aes e ncryption /d ecryption ................................................................................8 4.6 p eripheral f eatures .................................................................................................................8 4.7 l ow p ower ............................................................................................................................... ...8 4.8 2.4 gh z r adio with baseband modem .....................................................................................9 5 absolute maximum ratings.....................................................................................10 6 operating co nditions .................................................................................................10 6.1 cc2510f x o perating conditions .............................................................................................10 6.2 cc2511f x o perating conditions ..............................................................................................10 7 electrical spec ifications.......................................................................................11 7.1 g eneral c haracteristics ......................................................................................................12 7.2 rf r eceive s ection ..................................................................................................................13 7.3 rf t ransmit s ection ...............................................................................................................14 7.4 26/48 mh z c rystal o scillator .............................................................................................15 7.5 32.768 k h z c rystal o scillator ............................................................................................15 7.6 l ow p ower rc o scillator .....................................................................................................16 7.7 h igh s peed rc o scillator .....................................................................................................16 7.8 f requency s ynthesizer c haracteristics ............................................................................17 7.9 a nalog t emperature s ensor ................................................................................................17 7.10 8-14 bit adc............................................................................................................................ ..18 7.11 c ontrol ac c haracteristics ................................................................................................19 7.12 spi ac c haracteristics ..........................................................................................................20 7.13 d ebug i nterface ac c haracteristics .................................................................................21 7.14 p ort o utputs ac c haracteristics .......................................................................................21 7.15 t imer i nputs ac c haracteristics .........................................................................................22 7.16 dc c haracteristics ................................................................................................................22 8 pin and i/o port configuration .............................................................................23 9 circuit desc ription ......................................................................................................27 9.1 cpu and p eripherals ..............................................................................................................28 9.2 r adio ............................................................................................................................... ..........29 10 power cont rol................................................................................................................30 11 application circuit......................................................................................................31 11.1 b ias resistor ............................................................................................................................31 11.2 b alun and rf matching .........................................................................................................31 11.3 c rystal ............................................................................................................................... ......31 11.4 usb ( cc2511f x ) ..........................................................................................................................31 11.5 p ower supply decoupling .......................................................................................................31 12 8051 cpu....................................................................................................................... ............35 12.1 8051 cpu i ntroduction ..........................................................................................................35 12.2 r eset ............................................................................................................................... ...........35 12.3 m emory ............................................................................................................................... ......35 12.4 sfr r egisters ...........................................................................................................................39
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 3 of 252 12.5 cpu r egisters ..........................................................................................................................42 12.6 i nstruction s et s ummary ......................................................................................................44 12.7 i nterrupts ............................................................................................................................... .49 12.8 o scillators and clocks .........................................................................................................60 12.9 d ebug i nterface ......................................................................................................................60 12.10 ram............................................................................................................................ .......64 12.11 f lash m emory ..................................................................................................................64 12.12 m emory a rbiter ..............................................................................................................64 13 periphe rals.................................................................................................................... ....66 13.1 i/o ports ............................................................................................................................... .....66 13.2 dma c ontroller ....................................................................................................................84 13.3 16- bit t imer , t imer 1 ...............................................................................................................97 13.4 mac t imer (t imer 2) .............................................................................................................111 13.5 s leep t imer .............................................................................................................................11 3 13.6 8- bit t imer 3 and t imer 4 ......................................................................................................116 13.7 adc............................................................................................................................ ..............127 13.8 r andom n umber g enerator ................................................................................................133 13.9 aes c oprocessor ..................................................................................................................135 13.10 p ower m anagement ......................................................................................................140 13.11 p ower o n r eset .............................................................................................................144 13.12 w atchdog t imer ............................................................................................................145 13.13 usart .......................................................................................................................... ...147 13.14 i2s ............................................................................................................................ ........158 13.15 usb c ontroller ............................................................................................................166 13.16 f lash c ontroller .........................................................................................................184 14 crystal oscillator ...................................................................................................190 14.1 cc2510f x c rystal o scillator ..............................................................................................190 14.2 cc2511f x c rystal o scillator ..............................................................................................190 15 radio.......................................................................................................................... ...........191 15.1 c ommand strobes ..................................................................................................................191 15.2 r adio r egisters .....................................................................................................................193 15.3 i nterrupts ..............................................................................................................................1 93 15.4 tx/rx d ata t ransfer ..........................................................................................................195 15.5 d ata r ate p rogramming .....................................................................................................196 15.6 r eceiver c hannel f ilter b andwidth ................................................................................197 15.7 d emodulator , s ymbol s ynchronizer and d ata d ecision ..............................................197 15.8 p acket h andling h ardware s upport ................................................................................198 15.9 m odulation f ormats ...........................................................................................................202 15.10 r eceived s ignal q ualifiers and l ink q uality i nformation ..................................203 15.11 f orward e rror c orrection with i nterleaving .......................................................207 15.12 r adio c ontrol ...............................................................................................................208 15.13 f requency p rogramming .............................................................................................211 15.14 vco............................................................................................................................ ......211 15.15 o utput p ower p rogramming .......................................................................................212 15.16 s electivity g raphs .......................................................................................................213 15.17 a ntenna i nterface ........................................................................................................216 15.18 s ystem considerations and g uidelines .....................................................................216 15.19 r adio r egisters .............................................................................................................219 16 voltage regu lators .................................................................................................241 16.1 v oltage r egulator p ower - on ............................................................................................241 17 radio test output signals......................................................................................241 18 evaluation software ...............................................................................................243 19 register ov erview ......................................................................................................244 20 package descriptio n (qlp 36).................................................................................247
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 4 of 252 20.1 r ecommended pcb layout for package (qlp 36)............................................................248 20.2 p ackage thermal properties ...............................................................................................248 20.3 s oldering information ........................................................................................................248 20.4 t ray specification .................................................................................................................248 20.5 c arrier tape and reel specification ..................................................................................249 21 ordering information..............................................................................................249 22 general inform ation................................................................................................250 22.1 d ocument h istory ................................................................................................................250 22.2 p roduct s tatus d efinitions ................................................................................................250 23 address inform ation.................................................................................................251 24 ti worldwide tech nical support......................................................................251
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 5 of 252 1 abbreviations adc analog to digital converter aes advanced encryption standard agc automatic gain control arib association of radio industries and businesses bcd binary coded decimal ber bit error rate cbc cipher block chaining cbc-mac cipher block chaining message authentication code cca clear channel assessment ccm counter mode + cbc-mac cfb cipher feedback cfr code of federal regulations cmos complementary metal oxide semiconductor cpu central processing unit crc cyclic redundancy check ctr counter mode (encryption) cw continuous wave dac digital to analogue converter dma direct memory access dsm delta sigma modulator ecb electronic code book em evaluation module enob effective number of bits ep{0-5} usb endpoint 0-5 esd electro static discharge esr equivalent series resistance etsi european telecommunications standards institute fcc federal communications commission ffctrl fifo and frame control fifo first in first out hssd high speed serial debug i2s inter-ic sound i/o input / output i/q in-phase / quadrature-phase ieee institute of electrical and electronics engineers if intermediate frequency ioc i/o controller ism industrial, scientific and medical itu-t international tele communication union ? telecommunication standardization sector iv initialization vector kbps kilo bits per second kb 1024 bytes lfsr linear feedback shift register lna low-noise amplifier lo local oscillator lqi link quality indication lsb least significant bit / byte mac message authentication code mcu micro controller unit msb most significant byte na not available nc not connected ofb output feedback (encryption) pa power amplifier pcb printed circuit board per packet error rate pll phase locked loop pm{0-3} power mode 0-3 pmc power management controller por power on reset pwm pulse width modulator qlp quad leadless package ram random access memory rbw resolution bandwidth rcosc rc oscillator rf radio frequency rohs restriction on hazardous substances rssi receive signal strength indicator rtc real-time clock rx receive sck serial clock sfd start of frame delimiter sfr special function register sinad signal-to-noise and distortion ratio sof start of frame spi serial peripheral interface
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 6 of 252 sram static random access memory st sleep timer t/r transmit / receive tbd to be decided / to be defined tx transmit uart universal asynchronous receiver/transmitter usart universal synchronous/asynchronous receiver/transmitter usb universal serial bus vco voltage controlled oscillator vga variable gain amplifier wdt watchdog timer xosc crystal oscillator 2 references [1] nist fips pub 197: advanced encryption standard (aes), federal information processing standards publication 197, us department of commerce/n.i.s.t., november 26, 2001. available from the nist website. http://csrc.nist.gov/public ations/fips/fips197/fips-197.pdf [2] universal serial bus revision 2.0 specification. available from the usb implementors forum website. http://www.usb.org/developers/docs/ [3] i 2 s bus specification, philips semiconductors, available from the philips semiconductors website. http://www.semiconductors.philips.co m/acrobat_download/various/i2sbus.pdf [4] ieee std 1241-2000 , ieee standard for terminology and test methods for analog-to-digital converters. 3 register conventions each sfr register is described in a separate table. the table heading is given in the following format: register name (sfr address ) - register description. each rf register is described in a separate table. the table heading is given in the following format: xdata address: register name - register description all register descriptions include for each register bit a symbol denoted r/w describing the accessibility of the bit. the register values are always given in binary notation unless prefixed by ?0x? which indicates hexadecimal notation.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 7 of 252 symbol access mode r/w read/write r read only r0 read as 0 r1 read as 1 w write only w0 write as 0 w1 write as 1 h0 hardware clear h1 hardware set table 1: register bit conventions
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 8 of 252 4 features (continued from front page) 4.1 high-performance and low-power 8051-compatible microcontroller ? optimized 8051 core which typically gives 8x the performance of a standard 8051 ? dual data pointers ? in-circuit interactive debugging is supported for the iar embedded workbench through a simple two-wire serial interface 4.2 8/16/32 kb non-volatile program memory and 1/2/4 kb data memory ? 8, 16 or 32 kb of non-volatile flash memory, in-system programmable through a simple two-wire interface or by the 8051 core ? worst case flash memory endurance: 1000 write/erase cycles (applies per bit cell). ? programmable read and write lock of portions of flash memory for software security ? 1, 2 or 4 kb of internal sram 4.3 full-speed usb controller ( cc2511fx ) ? 5 bi-directional endpoints in addition to control endpoint 0 ? full-speed, 12 mbps transfer rate. ? support for bulk, interrupt and isochronous endpoints ? 1024 bytes of dedicated endpoint fifo memory. ? 8 ? 512 byte data packet size supported ? configurable fifo size for in and out direction of endpoint 4.4 i2s interface ? industry standard i2s interface for transfer of digital audio data ? full duplex ? mono and stereo support ? configurable sample rate and sample size ? support for -law compression and expansion ? typically used to connect to external dac or adc. 4.5 hardware aes encryption/decryption ? 128-bit aes supported in hardware coprocessor 4.6 peripheral features ? powerful dma controller ? power on reset ? battery monitor ? eight channel, 8-14 bit adc ? programmable watchdog timer ? real time clock with 32.768 khz crystal oscillator ? four timers: one general 16-bit timer, two general 8-bit timers, one mac timer. the 16-bit timer can also be used in delta- sigma modulator (dsm) mode. this allows the timer to produce a high quality audio output signal that only requires a low-cost passive external filter. ? two programmable usarts for master/slave spi or uart operation ? up to 21 configurable general-purpose digital i/o-pins ( cc2511fx has 19 general- purpose digital i/o-pins) ? random number generator 4.7 low power ? four flexible power modes for reduced power consumption ? only 0.5 a current consumption in standby mode, where external interrupts or the real-time counter can wake up the system ? 0.3 a current consumption in power down mode, where external interrupts can wake up the system ? system can wake up on external interrupt or real-time counter event
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 9 of 252 ? low-power fully static cmos design ? system clock sour ce can be 13 mhz rc oscillator or 26/48 mhz crystal oscillator. the 26/48 mhz oscillator is used when the radio is active. ? optional clock source for ultra-low power operation can be either a low-power rc oscillator or an optional 32.768 khz crystal oscillator ? very fast transition from sleep modes to active enable ultra low average power consumption in low duty-cycle systems 4.8 2.4 ghz radio with baseband modem ? based on the industry leading cc2500 radio core ? very few external components: totally on- chip frequency synthe sizer, no external filters or rf switch needed ? flexible support for packet oriented systems: on chip support for sync word detection, address check, flexible packet length and automatic crc handling. ? supports use of dma for both rx and tx. resulting in minima l cpu interference even on high data rates. ? programmable channel filter bandwidth ? 2-fsk, gfsk and msk supported. ? optional automatic whitening and de- whitening of data ? support for asynchronous transparent receive/transmit mode for backwards compatibility with existing radio communication protocols ? programmable carrier sense indicator ? programmable preamble quality indicator for detecting preambles and improved protection against sync word detection in random noise ? support for automatic clear channel assessment (cca) bef ore transmitting (for listen-before-talk systems) ? support for per-package link quality indication
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 10 of 252 5 absolute maximum ratings under no circumstances must the absolute maximu m ratings given in table 2 be violated. stress exceeding one or more of the limiting values may cause permanent damage to the device. parameter min max units condition supply voltage ?0.3 3.6 v all supply pins must have the same voltage voltage on any digital pin ?0.3 vdd+0.3, max 3.6 v input rf level +10 dbm storage temperature range ?50 150 c device not programmed solder reflow temperature 260 c according to ipc/jedec j-std-020c table 2: absolute maximum ratings caution! esd sensitive device. precaution should be used when handling the device in order to prevent permanent damage. 6 operating conditions 6.1 CC2510FX operating conditions the operating conditions for CC2510FX are listed table 3 in below. parameter min max unit condition operating ambient temperature, t a -40 85 c operating supply voltage 2.0 3.6 v all suppl y pins must have the same voltage table 3: operating conditions CC2510FX 6.2 cc2511fx operating conditions the operating conditions for cc2511fx are listed table 4 in below. parameter min max unit condition operating ambient temperature, t a 0 80 c operating supply voltage 3.0 3.6 v table 4 operating conditions cc2511fx
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 11 of 252 7 electrical specifications t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition power on reset voltage 1.1 v monitors the unregulated supply current consumption mcu active mode, static 500 a digital regulator on, high speed rcosc running. no radio, crystals, or peripherals. mcu active mode, dynamic 270 a/mhz digital regulator on, high speed rcosc running. no radio, crystals, or peripherals. 7.5 CC2510FX : mcu running at full speed (26 mhz), xosc running. no peripherals. mcu active mode, highest speed 7.0 ma cc2511fx : mcu running at full speed (24 mhz), xosc running. no peripherals. 20 CC2510FX : mcu running at full speed (26 mhz), xosc running, radio in rx mode. no peripherals. mcu active and rx mode, -100 dbm input 18 ma cc2511fx : mcu running at full speed (24 mhz), xosc running, radio in rx mode. no peripherals. 18 CC2510FX : mcu running at full speed (26 mhz), xosc running, radio in rx mode. no peripherals. mcu active and rx mode, -30 dbm input 16 ma cc2511fx : mcu running at full speed (24 mhz), xosc running, radio in rx mode. no peripherals. 23 CC2510FX : mcu running at full speed (26 mhz), xosc running, radio in tx mode. no peripherals. mcu active and tx mode, 0dbm 21 ma cc2511fx : mcu running at full speed (24 mhz), xosc running, radio in tx mode. no peripherals. power mode 1 187 a digital regulator on, high speed rcosc and crystal oscillator off. 32.768khz xo sc, por and st active. ram retention. power mode 2 0.5 a digital regulator off, high speed rcosc and crystal oscillator off. 32.768khz xo sc, por and st active. ram retention. power mode 3 0.3 a no clocks. ram retention. power on reset active. peripheral current consumption add to the figures above if the peripheral unit is activated timer 1 10 a/mhz when enabled timer 2 10 a/mhz when enabled timer 3 10 a/mhz when enabled timer 4 10 a/mhz when enabled sleep timer 0.5 a including low-power rc oscillator or 32.768khz xosc aes 50 a/mhz when encrypting/decrypting adc 0.9 ma when converting usart1 / usart2 12 a/mhz for each usart in use. not including current for driving i/o pins. dma 30 a/mhz when operating, not including current for memory access flash write 3 ma table 5: electrical specifications
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 12 of 252 7.1 general characteristics t a =25 c, vdd=3.0v if not hing else stated. parameter min typ max unit condition/note wake-up and timing pm1 ? pm0 31 ns digital regulator on, high speed rcosc or crystal oscillator running. entry from pm1 to pm0 takes one clock period. pm1 ? pm0 10 13 s digital regulator on, high speed rcosc and crystal oscillator off. start-up of high speed rcosc. pm1 ? pm0 rx/tx 195 s digital regulator on. crystal oscillator off. start-up of crystal oscillator and rf tx/rx begins. pm2/pm3 ? pm0 50 s digital regulator off, high speed rcosc and crystal oscillator off. start-up of regulator and high speed rcosc. radio part frequency range 2400 2483.5 mhz data rate 1.2 1.2 26 500 250 500 kbps kbps kbps 2-fsk gfsk and ook (shaped) msk (also known as differential offset qpsk) optional manchester encodi ng (halves the data rate). table 6: general characteristics
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 13 of 252 7.2 rf receive section t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note digital channel filter bandwidth 58 812 khz user programmable. the bandwidth limits are proportional to crystal frequency (given values assume a 26.0 mhz crystal). 2.4 kbps data rate, current optimized, mdmcfg2.dem_dcfilt_off = 1 (2-fsk, 1% packet error rate, 20 bytes pack et length, 203 khz digital channel filter bandwidth) ?105 CC2510FX : the typical current consumption is in this case 17.0 ma at sensitivity llimit. receiver sensitivity -107 dbm cc2511fx : the typical current consumption is in this case 17.0 ma at sensitivity llimit. saturation ?13 dbm adjacent channel rejection 23 db desired channel 3 db above the sensitivity limit. 250 khz channel spacing alternate channel rejection 31 db desired channel 3 db above the sensitivity limit. 250 khz channel spacing see figure 52 for plot of selectivity versus frequency offset 10 kbps data rate, current optimized, mdmcfg2.dem_dcfilt_off = 1 (2-fsk, 1% packet error rate, 20 bytes pack et length, 232 khz digital channel filter bandwidth) receiver sensitivity ?98 dbm the sensitivity can be improved to typically ?100 dbm by setting mdmcfg2.dem_dcfilt_off = 0 . the typical current consumption is in this case 17.3 ma at sensitivity llimit. saturation ?9 dbm adjacent channel rejection 18 db desired channel 3 db above the sensitivity limit. 250 khz channel spacing alternate channel rejection 25 db desired channel 3 db above the sensitivity limit. 250 khz channel spacing see figure 53 for plot of selectivity versus frequency offset 250 kbps data rate, mdmcfg2.dem_dcfilt_off = 0 (msk, 1% packet error rate, 20 bytes packet length, 600 khz digital channel filter bandwidth) ?91 CC2510FX receiver sensitivity -90 dbm cc2511fx saturation ?13 dbm adjacent channel rejection 21 db desired channel 3 db above the sensitivity limit. 750 khz channel spacing alternate channel rejection 30 db desired channel 3 db above the sensitivity limit. 750 khz channel spacing see figure 54 for plot of selectivity versus frequency offset 250 kbps data rate current optimized, mdmcfg2.dem_dcfilt_off = 1 (msk, 1% packet error rate, 20 bytes packet length, 540 khz digital channel filter bandwidth) receiver sensitivity ?86 dbm saturation ?13 dbm adjacent channel rejection 21 db desired channel 3 db above the sensitivity limit. 750 khz channel spacing alternate channel rejection 30 db desired channel 3 db above the sensitivity limit. 750 khz channel spacing see figure 55 for plot of selectivity versus frequency offset 500 kbps data rate, mdmcfg2.dem_dcfilt_off = 0 (msk, 1% packet error rate, 20 bytes packet length, 812 khz digital channel filter bandwidth) receiver sensitivity ?81 dbm saturation ?18 dbm adjacent channel rejection 14 db desired channel 3 db above the sensitivity limit. 1 mhz channel spacing
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 14 of 252 parameter min typ max unit condition/note alternate channel rejection 25 db desired channel 3 db above the sensitivity limit. 1 mhz channel spacing see figure 56 for plot of selectivity versus frequency offset general selectivity at 10 mhz offset 47 db desired channel at ?80 dbm. compliant with etsi en 300 440 class 2 receiver requirements. selectivity at 20 mhz offset 52 db desired channel at ?80 dbm. compliant with etsi en 300 440 class 2 receiver requirements. selectivity at 50 mhz offset 54 db desired channel at ?80 dbm. compliant with etsi en 300 440 class 2 receiver requirements. spurious emissions 25 mhz ? 1 ghz above 1 ghz ?57 ?47 dbm dbm table 7: rf receive section 7.3 rf transmit section t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note differential load impedance 80 + j74 ? differential impedance as seen from the rf-port (rf_p and rf_n) towards the antenna. follow the CC2510FX em reference design availabl e from chipcon?s website. output power, highest setting +1 dbm output power is programmable and is available across the entire frequency band delivered to 50 ? single-ended load via chipcon reference rf matching network. output power, lowest setting ?30 dbm output power is programmable and is available across the entire frequency band delivered to 50 ? single-ended load via chipcon reference rf matching network. spurious emissions 25 mhz ? 1 ghz above 1 ghz ?57 ?47 dbm dbm table 8: rf transmit parameters
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 15 of 252 7.4 26/48 mhz crystal oscillator 7.4.1 cc2510 crystal oscillator (26 mhz) t a =25 c, vdd=3.0v if nothi ng else is stated. parameter min typ max unit condition/note crystal frequency 24 26 27 mhz crystal frequency accuracy requirement 40 ppm this is the total tolerance including a) initial tolerance, b) ageing and c) temperature dependence. the acceptable crystal toleranc e depends on rf frequency and channel spacing / bandwidth. crystal shunt cap 1 5 7 pf load capacitance 10 13 20 pf esr 6 100 ? start-up time 212 us table 9: 26 mhz crystal oscillator parameters ( cc2510 ) 7.4.2 cc2511fx crystal oscillator (48 mhz) t a =25 c, vdd=3.0v if nothi ng else is stated. parameter min typ max unit condition/note crystal frequency 48 48 48 mhz crystal frequency accuracy requirement 40 ppm this is the total tolerance including a) initial tolerance, b) ageing and c) temperature dependence. the acceptable crystal toleranc e depends on rf frequency and channel spacing / bandwidth. crystal shunt cap 2 3 7 pf load capacitance 12 13 14 pf esr 30 60 ? start-up time 628 us table 10: 48 mhz crystal oscillator parameters ( cc2511fx ) 7.5 32.768 khz crystal oscillator t a =25 c, vdd=3.0v if nothi ng else is stated. parameter min typ max unit condition/note crystal frequency 32.768 khz crystal frequency accuracy requirement ppm esr 40 130 ? crystal shunt cap 0.9 2.0 pf load capacitance 12 16 pf start-up time 450 ms table 11: 32.768 khz crystal oscillator parameters
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 16 of 252 7.6 low power rc oscillator t a =25 c, vdd=3.0v if nothi ng else is stated. parameter min typ max unit condition/note calibrated frequency 34.6 34.7 36 khz calibrated rc oscillator frequency is xtal frequency divided by 750 frequency accuracy after calibration +0.3 -10 % temperature coefficient +0.4 % / c frequency drift when temperature changes after calibration supply voltage coefficient +3 % / v fr equency drift when supply voltage changes after calibration initial calibration time 2 ms w hen the rc oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. wake-up period 58 59650 seconds programmable, dependent on xtal frequency table 12: low power rc oscillator parameters 7.7 high speed rc oscillator t a =25 c, vdd=3.0v if nothi ng else is stated. parameter min typ max unit condition/note frequency 13 mhz calibrated high speed rc oscillator frequency is xtal frequency multiplied by 1/2 uncalibrated frequency accuracy 15 % calibrated frequency accuracy 1 % start-up time 10 s temperature coefficient -325 ppm / c frequency drift when temperature changes after calibration supply voltage coefficient 28 ppm / v fr equency drift when supply voltage changes after calibration initial calibration time 50 s when the high speed rc oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. table 13: high speed rc oscillator parameters
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 17 of 252 7.8 frequency synthesizer characteristics t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note programmed frequency resolution 397 f xosc / 2 16 412 hz 26-27 mhz crystal. synthesizer frequency tolerance 40 ppm given by crystal us ed. required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. rf carrier phase noise ?78 dbc/hz @ 50 khz offset from carrier rf carrier phase noise ?78 dbc/hz @ 100 khz offset from carrier rf carrier phase noise ?81 dbc/hz @ 200 khz offset from carrier rf carrier phase noise ?90 dbc/hz @ 500 khz offset from carrier rf carrier phase noise ?100 dbc/hz @ 1 mhz offset from carrier rf carrier phase noise ?108 dbc/hz @ 2 mhz offset from carrier rf carrier phase noise ?116 dbc/hz @ 5 mhz offset from carrier rf carrier phase noise ?127 dbc/hz @ 10 mhz offset from carrier pll turn-on / hop time 90 s time from leaving the idle state until arriving in the rx, fstxon or tx state, when not performing calibration. crystal oscillator running. pll rx/tx and tx/rx settling time 10 s settling time for the 1xif frequency step from rx to tx, and vice versa. pll calibration time 0.69 18739 0.72 0.72 xosc cycles ms calibration can be initiated manually, or automatically before entering or after leaving rx/tx. min/typ/max time is for 27/26/26 mhz crystal frequency. table 14: frequency synthesizer parameters 7.9 analog temperature sensor t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note output voltage at ?40 c 0.660 v output voltage at 0 c 0.755 v output voltage at +40 c 0.859 v output voltage at +80 c 0.958 v output voltage at +120 c 1.056 v temperature coefficient 2.54 mv/ c fitted from ?20 c to +80 c error in calculated temperature, calibrated 2 c from ?20 c to +80 c when using 2.54mv / c, after 1-point calibration at room temperature current consumption increase when enabled 0.3 ma table 15: analog temperature sensor parameters
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 18 of 252 7.10 8-14 bit adc t a =25 c, vdd=3.0v if nothing else stated. t he numbers given here are based on tests performed in accordance to the ieee std 1241-2000 [4]. parameter min typ max unit condition/note input voltage 0 avdd v avdd is voltage on avdd pin external reference voltage 0 avdd v avdd is voltage on avdd pin external reference voltage differential 0 avdd v avdd is voltage on avdd pin number of bits (enob) 7 13 bits the adc is a delta-sigma. effective resolution depends on sample rate used. differential input signal and reference assumed. offset - - - offset should be measured by sampling internal agnd 1 . 18 122 cc2510 using 26 mhz system clock. conversion time 20 132 s cc2511fx using 24 mhz system clock. differential nonlinearity (dnl) 3 0.3 lsb 8-bits setting integral nonlinearity (inl) 3 0.8 lsb 8-bits setting sinad 2 3 45 db 8-bits setting (sine input) 56 db 10-bits setting 66 db 12-bits setting 75 db 14-bits setting table 16: 8-14 bit adc characteristics 1 the offset value depends on several factors as: mode of operation, temperatur e, voltage, noise, reference etc. in order to sample with high accuracy, the dc value of internal agnd and avdd should be measured before starting the wanted sampling sequence. thus, knowing the statistical nonlinearity and effective number of bits, the co rrect sample value can easily be calculated. 2 the calculation assumes a differential input si gnal and a correlated differential reference. 3 dnl, inl and sinad are measured using dynamic characterisation methods by applying a sine wave input at p0.0 with avdd_soc as reference.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 19 of 252 7.11 control ac characteristics t a =85 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note 26 mhz CC2510FX : applies when 26 mhz crystal oscillator is used. maximum system clock is 13 mhz when high speed rc oscillator is used. system clock, f sysclk t sysclk = 1/ f sysclk 24 24 mhz cc2511fx : applies when 48 mhz crystal oscillator is used. maximum system clock is 13 mhz when high speed rc oscillator is used. reset_n low width 2.5 ns see item 1, figure 1. th is is the shortest pulse that is guaranteed to be recognized as a reset pin request. interrupt pulse width t sysclk see item 2, figure 1.thi s is the shortest pulse that is guaranteed to be recognized as an interrupt request. in pm2/3 the internal synchronizers are bypassed so this requirement does not apply in pm2/3. table 17: control inputs ac characteristics 1 2 2 reset_n px.n px.n figure 1: control inputs ac characteristics
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 20 of 252 7.12 spi ac characteristics t a =85 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note sck period see section 13.13.3 ns master. see item 1 figure 2 sck duty cycle 50% master. ssn low to sck 2*t sysclk see item 5 figure 2 sck to ssn high 30 ns see item 6 figure 2 miso setup 10 ns master. see item 2 figure 2 miso hold 10 ns master. see item 3 figure 2 sck to mosi 25 ns master. see item 4 figure 2, load = 10 pf sck period 100 ns slave. see item 1 figure 2 sck duty cycle 50% slave. mosi setup 10 ns slave. see item 2 figure 2 mosi hold 10 ns slave. see item 3 figure 2 sck to miso 25 ns slave. see item 4 figure 2, load = 10 pf table 18: spi ac characteristics figure 2: spi ac characteristics
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 21 of 252 7.13 debug interface ac characteristics t a =85 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note debug clock period 31.25 ns see item 1 figure 3 debug data setup 5 see item 2 figure 3 debug data hold 5 see item 3 figure 3 clock to data delay 10 see item 4 figure 3, load = 10 pf reset_n inactive after p2_2 rising 10 see item 5 figure 3 table 19: debug interface ac characteristics 1 3 2 debug clk p2_2 debug data p2_1 debug data p2_1 4 5 reset_n figure 3: debug interface ac characteristics 7.14 port outputs ac characteristics t a =85 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note p0, p1, p2port output pins, rise and fall time 10 load = 10 pf timing is with respect to 10% vdd and 90% vdd levels. table 20: port outputs ac characteristics
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 22 of 252 7.15 timer inputs ac characteristics t a =85 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. parameter min typ max unit condition/note input capture pulse width t sysclk synchronizers determine the shortest input pulse that can be recognized. the synchronizers operate from the current system clock rate table 21: timer inputs ac characteristics 7.16 dc characteristics the dc characteristics of CC2510FX/cc2511fx are listed in table 22 below. t a =25 c, vdd=3.0v if nothing else stated. measured on chipcon?s CC2510FX em reference design. digital inputs/outputs min typ max unit condition logic "0" input voltage 0 0.7 0.9 v logic "1" input voltage vdd-0.25 vdd vdd v logic "0" output voltage 0 0 0.25 v for up to 4ma output current on all pins except p1_0 and p1_1 which are up to 20 ma logic "1" output voltage vdd-0.25 vdd vdd v for up to 4ma output current on all pins except p1_0 and p1_1 which are up to 20 ma logic "0" input current n/a ?1 ?1 a input equals 0v logic "1" input current n/a 1 1 a input equals vdd i/o pin pull-up and pull-down resistor 17 20 23 k ? table 22: dc characteristics
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 23 of 252 8 pin and i/o port configuration the CC2510FX pinout is shown in figure 4 and table 23. see section 13.1 for details on the configuration of digital i/o ports. agnd exposed die attached pad reset_n dvdd p1_6 36 35 34 33 32 31 30 29 28 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18 p1_1 p1_0 p0_0 p0_1 p0_2 p0_3 p0_4 dvdd p0_5 p0_6 p0_7 p2_0 p2_1 p2_2 p2_3/xsoc32_q1 p2_4/xosc32_q2 avdd xosc_q2 avdd rf_n avdd avdd rbias xosc_q1 rf_p p1_3 p1_4 p1_5 p1_7 avdd_dreg guard p1_2 dcoupl figure 4: CC2510FX pinout top view note: the exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 24 of 252 pin pin name pin type description - gnd ground the exposed die attach pad must be connected to a solid ground plane 1 p1_2 d i/o port 1.2 2 dvdd power (digital) 2.0v-3.6v digi tal power supply for digital i/o 3 p1_1 d i/o port 1.1 4 p1_0 d i/o port 1.0 5 p0_0 d i/o port 0.0 6 p0_1 d i/o port 0.1 7 p0_2 d i/o port 0.2 8 p0_3 d i/o port 0.3 9 p0_4 d i/o port 0.4 10 dvdd power (digital) 2.0v-3.6v digi tal power supply for digital i/o 11 p0_5 d i/o port 0.5 12 p0_6 d i/o port 0.6 13 p0_7 d i/o port 0.7 14 p2_0 d i/o port 2.0 15 p2_1 d i/o port 2.1 16 p2_2 d i/o port 2.2 17 p2_3/xosc32_q1 d i/o port 2.3/32.768 khz crystal oscillator pin 1 18 p2_4/xosc32_q2 d i/o port 2.4/32.768 khz crystal oscillator pin 2 19 avdd power (analog) 2.0v-3.6v analog power supply connection 20 xosc_q2 analog i/o 26 mhz crystal oscillator pin 2 21 xosc_q1 analog i/o 26 mhz crystal o scillator pin 1, or external clock input 22 avdd power (analog) 2.0v-3.6v analog power supply connection 23 rf_p rf i/o positive rf input signal to lna in receive mode positive rf output signal from pa in transmit mode 24 rf_n rf i/o negative rf input signal to lna in receive mode negative rf output signal from pa in transmit mode 25 avdd power (analog) 2.0v-3.6v analog power supply connection 26 avdd power (analog) 2.0v-3.6v analog power supply connection 27 rbias analog i/o external precision bi as resistor for reference current 28 guard power (digital) power supply connection for digital noise isolation 29 avdd_dreg power (digital) 2.0v-3.6v digital po wer supply for digital core voltage regulator 30 dcoupl power decoupling 1.8v di gital power supply decoupling 31 reset_n di reset, active low 32 p1_7 d i/o port 1.7 33 p1_6 d i/o port 1.6 34 p1_5 d i/o port 1.5 35 p1_4 d i/o port 1.4 36 p1_3 d i/o port 1.3 table 23: CC2510FX pinout overview
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 25 of 252 the cc2511fx pinout is shown in figure 5 and table 24. see section 13.1 for details on the configuration of digital i/o ports. agnd exposed die attached pad reset_n dvdd p1_6 36 35 34 33 32 31 30 29 28 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18 p1_1 p1_0 p0_0 p0_1 p0_2 p0_3 p0_4 dp dm dvdd p0_5 p2_0 p2_1 p2_2 p2_3/xsoc32_q1 p2_4/xosc32_q2 avdd xosc_q2 avdd rf_n avdd avdd r_bias xosc_q1 rf_p p1_3 p1_4 p1_5 p1_7 avdd_dreg guard p1_2 dcoupl figure 5: cc2511fx pinout top view note: the exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 26 of 252 pin pin name pin type description - gnd ground the exposed die attach pad must be connected to a solid ground plane 1 p1_2 d i/o port 1.2 2 dvdd power (digital) 2.0v-3.6v digi tal power supply for digital i/o 3 p1_1 d i/o port 1.1 4 p1_0 d i/o port 1.0 5 p0_0 d i/o port 0.0 6 p0_1 d i/o port 0.1 7 p0_2 d i/o port 0.2 8 p0_3 d i/o port 0.3 9 p0_4 d i/o port 0.4 10 dp usb i/o usb differential data bus plus 11 dm usb i/o usb differential data bus minus 12 dvdd power (digital) 2.0v-3.6v digi tal power supply for digital i/o 13 p0_5 d i/o port 0.5 14 p2_0 d i/o port 2.0 15 p2_1 d i/o port 2.1 16 p2_2 d i/o port 2.2 17 p2_3/xosc32_q1 d i/o port 2.3/32.768 khz crystal oscillator pin 1 18 p2_4/xosc32_q2 d i/o port 2.4/32.768 khz crystal oscillator pin 2 19 avdd power (analog) 2.0v-3.6v analog power supply connection 20 xosc_q2 analog i/o 48 mhz crystal oscillator pin 2 21 xosc_q1 analog i/o 48 mhz crystal o scillator pin 1, or external clock input 22 avdd power (analog) 2.0v-3.6v analog power supply connection 23 rf_p rf i/o positive rf input signal to lna in receive mode positive rf output signal from pa in transmit mode 24 rf_n rf i/o negative rf input signal to lna in receive mode negative rf output signal from pa in transmit mode 25 avdd power (analog) 2.0v-3.6v analog power supply connection 26 avdd power (analog) 2.0v-3.6v analog power supply connection 27 rbias analog i/o external precision bi as resistor for reference current 28 guard power (digital) power supply connection for digital noise isolation 29 avdd_dreg power (digital) 2.0v-3.6v digital po wer supply for digital core voltage regulator 30 dcoupl power decoupling 1.8v digital power supply decoupling 31 reset_n di reset, active low 32 p1_7 d i/o port 1.7 33 p1_6 d i/o port 1.6 34 p1_5 d i/o port 1.5 35 p1_4 d i/o port 1.4 36 p1_3 d i/o port 1.3 table 24: cc2511fx pinout overview
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 27 of 252 9 circuit description figure 6: CC2510FX/cc2511fx block diagram
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 28 of 252 a block diagram of CC2510FX/cc2511fx is shown in figure 6. the modules can be roughly divided into one out of three categories: cpu- related modules, radio-related modules and modules related to power, test and clock distribution. in the following subsections, a short description of each module that appears in figure 6 is given. 9.1 cpu and peripherals the 8051 cpu core is a single-cycle 8051- compatible core. it has three different memory access buses (sfr, data and code/xdata), a debug interface and an 18- input extended interrupt unit. see section 12 for details. the memory crossbar/arbitrator is at the heart of the system as it connects the cpu and dma controller with the physical memories and all peripherals through the sfr bus. the memory arbitrator has four memory access points, which can access three physical memories: a 1/2/4 kb sram, 8/16/32 kb flash memory or sfr registers. the memory arbitrator is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. the sfr bus is drawn conceptually in the block diagram as a common bus that connects all hardware peripherals to the memory arbitrator. the sfr bus also provides access to the radio registers in the radio register bank even though these are indeed mapped into xdata memory space. the 1/2/4 kb sram maps to the data memory space and part of the xdata/code memory spaces. the memory is an ultra-low- power sram that retains its contents even when the digital part is powered off (power modes 2 and 3). the 8/16/32 kb flash block provides in-circuit programmable non-volatile program memory for the device and maps into the code and xdata memory spaces. writing to the flash block is performed through a flash controller that allows page-wise (1024 byte) erasure and byte-wise reprogramming. see section 13.16 for details. a versatile five-channel dma controller is available in the system. it accesses memory using a unified memory space (xdata) and has therefore access to all physical memories. each channel is configured (trigger event, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) with dma descriptors anywhere in memory. many of the hardware peripherals rely on the dma controller for efficient operation (aes core, flash controller, usarts, timers and adc interface) by performing data transfers between a single sfr address and flash/sram. see section 13.2 for details. the interrupt controller services 18 interrupt sources, divided into six interrupt groups, each of which is associated with one out of four interrupt priorities. an interrupt request is serviced even if the device is in a sleep mode (power modes 1-3) by bringing the CC2510FX/cc2511fx back to active mode (power mode 0). the debug interface implements a proprietary two-wire serial interface that is used for in- circuit debugging. through this debug interface it is possible to perform an erasure of the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051 core, set code breakpoints, and single step through instructions in the code. using these techniques, it is possible to elegantly perform in-circuit debugging and external flash programming. see section 12.9 for details. the i/o-controller is responsible for all general-purpose i/o pins. the cpu can configure whether peripheral modules control certain pins or whether they are under software control. if uses as i/o whether each pin is configured as an input or output, and if a pull-up or pull-down resistor in the pad is connected. each peripheral that connects to the i/o-pins can choose between two different locations to ensure flexibility in various applications. see section 13.1 for details. the sleep timer is an ultra-low power timer that counts 32.768 khz crystal oscillator or 32 - 34.6667 khz rc oscillator periods. the sleep timer runs continuously in all operating modes except power mode 3. it can be configured in one of several resolution modes, to strike the right balance between timer resolution and timeout period. typical uses for it is as a real- time counter that runs regardless of operating mode (except power mode 3) or as a wakeup timer to get out of power modes 1 or 2. see section 13.5 for details. a built-in watchdog timer allows the CC2510FX/cc2511fx to reset itself in case the
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 29 of 252 firmware hangs. when enabled, the watchdog timer must be cleared periodically, otherwise it will reset the device when it times out. see section 13.12 for details. timer 1 is a 16-bit timer with timer/counter/pwm functionality. it has a programmable prescaler, a 16-bit period value and three individually programmable counter/capture channels each with a 16-bit compare value. each of the counter/capture channels can be used as pwm outputs or to capture the timing of edges on input signals. a second order sigma-delta noise shaper mode is also supported for audio applications. see section 13.3 for details. timer 2 (mac timer) is specially designed to support time-slotted protocols in software. the timer has a configurable timer period and 18- bit tunable prescaler range. see section 13.4 for details. timers 3 and 4 are 8-bit timers with timer/counter/pwm functionality. they have a programmable prescaler, an 8-bit period value and one programmable counter/capture channel with an 8-bit compare value. each of the counter/capture channels can be used as pwm outputs or to capture the timing of edges on input signals. see section error! reference source not found. for details. usart 0 and 1 are each configurable as either an spi master/slave or a uart. they provide double buffering on both rx and tx to support high-throughput full-duplex applications. each has its own high-precision baud-rate generator thus leaving the ordinary timers free for other uses. see section 13.13 for details. the aes encryption/decryption core allows the user to encrypt and decrypt data using the aes algorithm with 128-bit keys. see section 13.9 for details. the adc supports 8 to 14 bits of resolution in a 30 khz to 4 khz bandwidth respectively. dc and audio conversion with up to eight input channels (port 0) is possible. the inputs can be selected as single ended or differential. the reference voltage can be internal, avdd, or a single ended or differential external signal. the adc also has a temperature sensor input channel. the adc can automate the process of periodic sampling or conversion over a sequence of channels. see section 13.7 for details. the usb allows the cc2511fx to implement a full-speed usb 2.0 compatible device. the usb has a dedicated 1 kb sram that is used for the endpoint fifos. 5 endpoints are available in addition to control endpoint 0. each of these endpoints must be configured as bulk/interrupt or isochronous and can be used as in, out or in /out. double buffering of packets is also supported for endpoints 1-5. the maximum fifo memory available for each endpoint is as follows: 32 bytes for endpoint 0, 32 bytes for endpoint 1, 64 bytes for endpoint 2, 128 bytes for endpoint 3, 256 bytes for endpoint 4 and 512 bytes for endpoint 5. when an endpoint is used as in/out the fifo memory available for the endpoint can be distributed between in and out depending on the demands of the application. the usb does not exist on the CC2510FX . see section 13.15 for details. the i2s can be used to send/receive audio samples to/from an external sound processor or dac and may operate at full or half duplex. samples of up to 16-bits resolution can be used although the i2s can be configured to send more low order bits if necessary to be compliant with the resolution of the receiver. (up to 32 bit) the maximum bit-rate supported is 3.5 mbps. the i2s can be configured as a master or slave device and supports both mono and stereo. automatic -law expansion and compression can also be configured. see section 13.14 on page 158 for details. 9.2 radio CC2510FX/cc2511fx features an rf transceiver based on the industry-leading cc2500 , requiring very few external components. see section 15 for details.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 30 of 252 10 power control the CC2510FX/cc2511fx has four power modes, called pm0, pm1, pm2 and pm3. pm0 is the active mode while pm3 has the lowest power consumption. the power modes are shown in table 25 together with voltage regulator and oscillator options. power mode high speed oscillator low-speed oscillator voltage regulator (digital) configuration a none b 26/48 mhz xosc c hs rcosc a none b low power rcosc c 32.768 khz xosc pm0 b, c b, c on pm1 a b, c on pm2 a b, c off pm3 a a off table 25: power modes pm0 : the full functional mode. the voltage regulator to the digital core is on and either the high speed rc oscillato r or the 26/48 mhz crystal oscillator or both are running. either the low power rc oscillato r or the 32.768 khz crystal oscillator is running. pm1 : the voltage regulator to the digital part is on. neither the 26/48 mh z crystal oscillator nor the high speed rc oscilla tor is running. either the low power rc oscilla tor or the 32.768 khz crystal oscillator is running. the system will go to pm0 on reset or an external interrupt or when the sleep timer expires. pm2 : the voltage regulator to the digital core is turned off. neither the 26/48 mhz crystal oscillator nor the high speed rc oscillator is running. either the low power rc oscillator or the 32.768 khz crystal oscillator is running. the system will go to pm0 on reset or an external interrupt or when the sleep timer expires. the cc2511fx will lose all usb state information when pm2 is entered. thus, pm2 should not be used with usb. pm3 : the voltage regulator to the digital core is turned off. none of the oscillators are running. the system will go to pm0 on reset or an external interrupt. the cc2511fx will lose all usb state information when pm3 is entered. thus, pm3 should not be used with usb .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 31 of 252 11 application circuit this section describes the recommended application circuit for the rf part of the CC2510FX/cc2511fx , together with crystal oscillator connections and usb. only a few external components are required for using the CC2510FX/cc2511fx rf transceiver. the recommended application circuit for CC2510FX is shown in figure 7. the recommended application circuits for cc2511fx are shown in figure 8 and figure 9. the first circuit uses a fundamental crystal and the second uses a 3 rd overtone crystal. the external components are described in table 26, and typical values are given in table 27. notice that all application circuits are shown excluding supply decoupling capacitors and digital i/o. 11.1 bias resistor the bias resistor r271 is used to set an accurate bias current. it is very important to use the specified tolerance for this resistor. 11.2 balun and rf matching c232, c242, l231 and l241 form the recommended balun that converts the differential rf port on CC2510FX/cc2511fx to a single-ended rf signal. (c241 and c231 are also needed for dc blocking). together with an appropriate lc network, the balun components also transform the impedance to match a 50 ? antenna (or cable). component values for the rf balun and lc network are easily found using the smartrf ? studio software. suggested values are listed in table 27. the balun and lc filter component values and their placement are important to keep the performance optimized. it is recommended to follow the cc2510em / cc2511dongle reference design. 11.3 crystal the crystal oscillator for the CC2510FX uses an external crystal x1, with two loading capacitors (c201 and c211). see section 14 on page 190 for details. the cc2511fx should use a 48 mhz fundamental (x3) or a 48 mhz 3 rd overtone low cost external crystal (x4). depending on the option selected, different loading capacitors (c203, c214) or (c202, c212, c213) must be used. when x4 is used, an inductor, l281, must also be connected in series with c212. the circuit also shows the connections for the optional 32.768 khz crystal oscillator, with external crystal x2 and loading capacitors c181 and c171. this crystal oscillator is used by the sleep timer providing a real-time clock function and is not required for radio operation. the sleep timer may use the internal rc oscillator as an alternative to x2. the internal rc oscillator is less accu rate but saves cost and board space. when not using x2 p2_3 and p2_4 may be used as general io pins. 11.4 usb ( cc2511fx ) for the cc2511fx the dp and dm pins need series resistors r262 and r263 for impedance matching and the dp line must have a pull-up resistor, r264. the series resistors should match the 90 ? +/- 5% characteristic impedance of the usb bus. notice that the pull-up resistor must be tied to a voltage source between 3.0 and 3.6 v (typically 3.3v). the voltage source must be derived from or controlled by the v bus power supply, provided by the usb cable, such that when v bus is removed, the pull-up resistor does not provide current to the d+ line. the pull-up resistor may be connected direcly between v bus and the d+ line. or if the cc2511fx firmware need the ability to disconnect from the usb bus,, a i/o pin on the cc2511fx can be used to control the pull-up resistor. 11.5 power supply decoupling the power supply must be properly decoupled close to the supply pins. note that decoupling capacitors are not shown in the application circuit. the placement and the size of the decoupling capacitors are very important to achieve the optimum performance. chipcon provides a reference design that should be followed closely.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 32 of 252 figure 7: application circuit for CC2510FX figure 8: application circuit for cc2511fx with usb and fundamental crystal
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 33 of 252 figure 9: application circuit for cc2511fx with usb and 3 rd overtone crystal component description c301 decoupling capacitor for on-chip voltage regulator to digital part c203/c214 crystal loading capac itors (fundamental crystal) c202/c212/c213 crystal loading capacitors (3 rd overtone crystal) c201/c211 crystal loading capacitors, see section 14 on page 190 for details c231/c241 rf balun dc blocking capacitors c232/c241 rf balun/matching capacitors c233/c234 rf lc filter/matching capacitors c181/c171 crystal loading c apacitors if x2 is used. l231/l241 rf balun/matching inductors (ine xpensive multi-layer type) l232 rf lc filter inductor (i nexpensive multi-layer type) l281 crystal inductor r271 56 k ? resistor for internal bias current reference, 1% tolerance r264 d+ pullup resistor r262/r263 d+ / d- series re sistors for impedance matching x1 26 mhz -27 mhz crystal, see section 14 on page 190 for details x2 32.768 khz crystal, optional x3 48 mhz crystal (fundamental) x4 48 mhz crystal (3 rd overtone) table 26: overview of external components (excluding supply decoupling capacitors)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 34 of 252 component value c301 100 nf10%, 0402 x5r c203/c214 33 pf c202 56 pf c212 10 nf c213 33 pf c201, c211 27 pf5%, 0402 np0 c231, c241 100 pf5%, 0402 np0 c171, c181 15 pf5%, 0402 np0 c232, c242 1.0 pf0.25 pf, 0402 np0 c233 1.8 pf0.25 pf, 0402 np0 c234 1.5 pf0.25 pf, 0402 np0 l231, l232, l241 1.2 nh0.3 nh, 0402 monolithic, murata lqg-15 series l281 470 nh10%, murata lqm18nnr47k00 r271 56 k ? 1%, 0402 r264 1.5 k ? 5% r262/r263 x1 26.0 mhz surface mount crystal x2 32.768 khz surface mount crystal (optional) x3 48.0 mhz surface mount crystal (fundamental) x4 48.0 mhz surface mount crystal (3 rd overtone) table 27: bill of materials f or the CC2510FX/cc2511fx applicat ion circuits (subject to changes)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 35 of 252 12 8051 cpu this section describes the 8051 cpu core, with interrupts, memory and instruction set. 12.1 8051 cpu introduction the CC2510FX/cc2511fx includes an 8-bit cpu core, which is an enhanced version of the industry standard 8051 core. the enhanced 8051 core uses the standard 8051 instruction set. instructions execute faster than the standard 8051 due to the following: ? one clock per instruction cycle is used as opposed to 12 clocks per instruction cycle in the standard 8051. ? redundant bus states are eliminated. ? parallel execution of fetch and execute phases. since an instruction cycle is aligned with memory fetch when possible, most of the single byte instructions are performed in a single clock cycle. in addition to the speed improvement, the enhanced 8051 core also includes architectural enhancements: ? dual data pointers ? extended 18-source interrupt unit the 8051 core is object code compatible with the industry standard 8051 microcontroller. that is, object code compiled with an industry standard 8051 compiler or assembler executes on the 8051 core and is functionally equivalent. however, because the 8051 core uses a different instruction timing than many other 8051 variants, existing code with timing loops may require modification. also, because the peripheral units such as timers and serial ports differ from those on other 8051 cores, code which includes instructions using the peripheral units sfrs w ill not work correctly. 12.2 reset the CC2510FX/cc2511fx has three reset sources. the following events generate a reset: ? forcing reset_n input pin low ? a power-on reset condition ? watchdog timer reset condition the initial conditions after a reset are as follows: ? i/o pins are configured as inputs with pull-up, except p1_0 and p1_1. ? cpu program counter is loaded with 0x0000 and program execution starts at this address ? all peripheral registers are initialized to their reset values (refer to register descriptions) ? watchdog timer is disabled 12.3 memory the 8051 cpu has four different memory spaces: code . a 16-bit read-only memory space for program memory. data . an 8-bit read/write data memory space, which can be directly or indirectly accessed by a single cpu instruction. the lower 128 bytes of the data memory space can be addressed either directly or indire ctly, the upper 128 bytes only indirectly. xdata . a 16-bit read/write data memory space access to which usually requires 4-5 cpu instruction cycles. access to xdata memory is also slower in hardware than data access as the code and xdata memory spaces share a common bus on the cpu core and instruction pre-fetch from code can thus not be performed in parallel with xdata accesses. sfr . a 7-bit read/write register memory space, which can be directly accessed by a single cpu instruction. for sfr registers whose address is divisible by eight, each bit is also individually addressable. the four different memory spaces are distinct in the 8051 architec ture, but are partly overlapping in the CC2510FX/cc2511fx to ease dma transfers and hardware debugger operation. how the different memory spaces are mapped onto the three physical memories (8/16/32 kb flash program memory, 1/2/4 kb sram and
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 36 of 252 hardware registers) is desc ribed in section 12.3.2. 12.3.1 memory map this section gives an overview of the memory map. the memory differs from the standard 8051 memory map in two important aspects, as described below. first, all the physical memories code, data, xdata, radio register, usb registers and most of the hardwar e sfr registers are mapped into a unified xdata memory space as shown in figure 10. note that 128 upper bytes of data are located at a different xdata location than the sfr registers and they can be accessed directly. mapping all the memory spaces to xdata is primarily done to allow the dma controller access them, thus allowing dma transfers between these areas. this also means that any mcu operation that read/write or manipulate a xdata variable can be used on the entire unified xdata memory space, except writing to or changing data in the 8/16/32 kb code memory space (flash). the hardware sfr register shown in gray in table 29 are not mapped into the xdata memory space, thus they can not be accessed from the dma. secondly, the code memory space is mapped identically to the xdata. see figure 10. this is primarily to done to allow program execution out of the sram/xdata. details about the mapping of all 8051 memory spaces are given in the next section. unimplemented cc2510/2511 xdata memory space 32 kb flash physical memory 4 kb sram hardware radio / i2s registers xdata (and unified code) memory space data memory space s f r m e m o r y s p a c e 8051 memory spaces non-volatile program memory 32 kb 0x0000 hardware registers fast access ram 0xe000 slow access ram / program memory in ram 0xf000 0xffff 0x0000 0x7fff 0xff 0x80 0xff 0x00 hardware sfr registers 0xdf00 0xdf80 0xdfff 0xfeff 0xff00 0xffff unimplemented 0x8000 0xefff usb registers ( ) 0xde3f 0xde00 usb registers ( ) unimplemented 0xde40 0xddff 0xdeff figure 10: CC2510FX/cc2511fx xdata memory space (cc2510f32/cc2511f32 shown here) 12.3.2 memory space this section describes the details of each cpu memory space. the caption of each chapter refer to the memory spaces in a standard 8051, any differences between the standard 8051 and CC2510FX/cc2511fx is described. xdata memory space . on a standard 8051 this memory space would hold any extra ram available (in addition to the 128/256 byte data)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 37 of 252 the CC2510FX/cc2511fx has a total of 1, 2 or 4 kb sram, starting at address 0xf000. compilers/assemblers must take into consideration that the first address of usable sram starts at address 0xf000 instead of 0x0000. the 256 bytes from 0xff00 to 0xffff are the data memory mapped to xdata. these bytes are also reached through the data memory space. the 350 bytes of xdata in location 0xfda2- 0xfeff on cc2510f32 and cc2511f32 do not retain data when power modes pm2/3 are entered. however these bytes may be used in pm0 and pm1 on the f32 versions. the rest of the sram will retain its contents in pm0 to 3. refer to section 13.10 on page 140 for a detailed description of power modes. see table 28 for an overview of the sram and flash memory map. data ram no retention ram xdata ram flash memory cc251xf8 0xff00 ? 0xffff ? 0xf0 00 ? 0xf2ff 0x0000 ? 0x1fff cc251xf16 0xff00 ? 0xffff ? 0xf0 00 ? 0xf6ff 0x0000 ? 0x3fff cc251xf32 0xff00 ? 0xffff 0xfda2 ? 0x feff 0xf000 ? 0xfda9 0x0000 ? 0x7fff table 28 sram and flash memory map in addition the following is mapped into the xdata memory space: ? the 8, 16 and 32 kb flash program memory (code) is mapped into the address ranges 0x0000-0x1fff, 0x0000-0x3fff and 0x0000-0x7fff respectively. ? radio registers are mapped into address range 0xdf00-0xdf3d. ? i2s registers are mapped into the address range 0xdf40-0xdf48. ? all sfr except the registers shown in gray in table 29. are mapped into address range 0xdf80-0xdfff. ? the usb registers are mapped into the address range 0xde00-0xde3f on the cc2511fx , but are not implemented on the CC2510FX . this memory mapping allows the dma controller (and the cpu) access to all the physical memories in a single unified address space. code memory space . on a standard 8051 this memory space would hold the program memory, where the mcu reads the program/instructions. the CC2510FX/cc2511fx has 8, 16 or 32 kb flash program memory intended to hold the mcu program. the flash is mapped into code and starts at address 0x0000. in addition all other memory spaces are mapped into the code memory space. the mapping is identical to xdata (see the xdata memory space) thus the CC2510FX/cc2511fx mcu may execute a program stored in sram. this allows the program to be easily updated without writing to flash (which have a limited erase/write cycles) this is particularly useful on the cc2511fx , where parts of the firmware can be downloaded from the windows usb driver. executing a program from sram instead of flash will also result in a lower power consumption and may be interesting for battery powered devices. data memory space . the data memory space of CC2510FX/cc2511fx is identical to a standard 8051, with 256 byte of ram accessible through the 8-bit address range of data
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 38 of 252 memory. just like a standard 8051 the upper 128 byte share address with the sfr and can only be accessed indirectly, the stack is normally located here. the lower 48 bytes are reserved, and hold 4 register banks used by the mcu. the 16 bytes on addresses 0x20 to 0x2f are bit addressable. the data memory will retain its contents in pm0 to 3 the data memory can be accessed through the xdata and code memory spaces at the address ranges 0xff00-0xffff. sfr memory space . the sfr memory space is identical to a standard 8051. the 128-entry hardwar e register area is accessed through this memory space. unlike a standard 8051, the sfr registers are also accessible through the xdata and code address space at the address range 0xdf80-0xdfff. some cpu-specific sfr registers reside inside the cpu core and can only be accessed using the sfr memory space and not through the duplicate mapping into xdata/code memory space, these registers are shown in gray in table 29. 12.3.3 data pointers the CC2510FX/cc2511fx has two data pointers, dptr0 and dptr1 to accelerate the movement of data blocks to/from memory. the data pointers are generally used to access code or xdata space e.g. movc a,@a+dptr mov a,@dptr . the data pointer select bit, bit 0 in the data pointer select register dps, chooses which data pointer shall be the active one during execution of an instruct ion that uses the data pointer, e.g. in one of the above instructions. the data pointers are two bytes wide consisting of the following sfrs: ? dptr0 ? dph0:dpl0 ? dptr1 ? dph1:dpl1 dph0 (0x83) ? data pointer 0 high byte bit name reset r/w description 7:0 dph0[7:0] 0 r/w data pointer 0, high byte dpl0 (0x82) ? data pointer 0 low byte bit name reset r/w description 7:0 dpl0[7:0] 0 r/w data pointer 0, low byte dph1 (0x85) ? data pointer 1 high byte bit name reset r/w description 7:0 dph1[7:0] 0 r/w data pointer 1, high byte dpl1 (0x84) ? data pointer 1 low byte bit name reset r/w description 7:0 dpl1[7:0] 0 r/w data pointer 1, low byte dps (0x92) ? data pointer select bit name reset r/w description 7:1 - 0x00 r0 not used
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 39 of 252 bit name reset r/w description 0 dps 0 r/w data pointer select. selects active data pointer. 0 dptr0 1 dptr1 12.3.4 xdata memory access the CC2510FX/cc2511fx provides an additional sfr register mpage . this register is used during instructions movx a,@ri and movx @ri,a mpage gives the 8 most significant address bits, while the register ri gives the 8 least significant bits. in some 8051 implementations, this type of xdata access is performed using p2 to give the most significant address bits. existing software may therefore have to be adapted to make use of mpage instead of p2 . mpage (0x93)? memory page select bit name reset r/w description 7:0 mpage[7:0] 0x00 r/w memory page, high-order bits of address in movx instruction 12.4 sfr registers the special function registers (sfrs) control several of the features of the 8051 cpu core and/or peripherals. many of the 8051 core sfrs are identical to the standard 8051 sfrs. however, there are additional sfrs that control features that are not available in the standard 8051. the additional sfrs are used to interface with the peripheral units and rf transceiver. table 29 shows the address to all sfrs in CC2510FX/cc2511fx . the 8051 internal sfrs are shown with grey background, while the the other sfrs are specific to CC2510FX/cc2511fx . note: all internal sfrs (shown with grey background in table 29), can only be accessed through sfr space as these registers are not mapped into xdata space. table 30 lists the additional sfrs that are not standard 8051 peripheral sfrs or cpu- internal sfrs. the additional sfrs are described in the relevant sections for each peripheral function.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 40 of 252 8 bytes 80 p0 sp dpl0 dph0 dpl1 dph1 u0csr pcon 87 88 tcon p0ifg p1ifg p2ifg pictl p1ien - p0inp 8f 90 p1 rfim dps mpage - endian - - 97 98 s0con - ien2 s1con t2ct t2pr t2ctl - 9f a0 p2 worirq worctl worevt0 worevt1 wortime0 wortime1 - a7 a8 ien0 ip0 - fwt faddrl fa ddrh fctl fwdata af b0 - encdi encdo enccs a dccon1 adccon2 adccon3 - b7 b8 ien1 ip1 adcl adch rndl rndh sleep - bf c0 ircon u0dbuf u0baud - u0ucr u0gcr clkcon memctr c7 c8 - wdctl t3cnt t3ctl t3cctl0 t3cc0 t3cctl1 t3cc1 cf d0 psw dmairq dma1cfgl dma1cfgh dma0cfgl dma0cfgh dmaarm dmareq d7 d8 timif rfd t1cc0l t1cc0h t1cc1l t1cc1h t1cc2l t1cc2h df e0 acc rfst t1cntl t1cnth t1ctl t1cctl0 t1cctl1 t1cctl2 e7 e8 ircon2 rfif t4cnt t4ctl t4cctl0 t4cc0 t4cctl1 t4cc1 ef f0 b percfg adccfg p0sel p1sel p2sel p1inp p2inp f7 f8 u1csr u1dbuf u1baud u1ucr u1gcr p0dir p1dir p2dir ff table 29: sfr address overview table 30: CC2510FX/cc2511fx specific sfr overview register name sfr address module description adccon1 0xb4 adc adc control 1 adccon2 0xb5 adc adc control 2 adccon3 0xb6 adc adc control 3 adcl 0xba adc adc data low adch 0xbb adc adc data high rndl 0xbc adc random number generator data low rndh 0xbd adc random number generator data high encdi 0xb1 aes encryption/decryption input data encdo 0xb2 aes encryption/decryption output data enccs 0xb3 aes encryption/decryption control and s tatus dmairq 0xd1 dma dma interrupt flag dma1cfgl 0xd2 dma dma channel 1-4 configuration address low dma1cfgh 0xd3 dma dma channel 1-4 configuration address high dma0cfgl 0xd4 dma dma channel 0 configuration address low dma0cfgh 0xd5 dma dma channel 0 configuration address high dmaarm 0xd6 dma dma channel arm dmareq 0xd7 dma dma channel start request and status fwt 0xab flash flash write timing faddrl 0xac flash flash address low faddrh 0xad flash flash address high
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 41 of 252 register name sfr address module description fctl 0xae flash flash control fwdata 0xaf flash flash write data p0ifg 0x89 ioc port 0 interrupt status flag p1ifg 0x8a ioc port 1 interrupt status flag p2ifg 0x8b ioc port 2 interrupt status flag pictl 0x8c ioc port pins interrupt mask and edge p1ien 0x8d ioc port 1 interrupt mask p0inp 0x8f ioc port 0 input mode percfg 0xf1 ioc peripheral i/o control adccfg 0xf2 ioc adc input configuration p0sel 0xf3 ioc port 0 function select p1sel 0xf4 ioc port 1 function select p2sel 0xf5 ioc port 2 function select p1inp 0xf6 ioc port 1 input mode p2inp 0xf7 ioc port 2 input mode p0dir 0xfd ioc port 0 direction p1dir 0xfe ioc port 1 direction p2dir 0xff ioc port 2 direction memctr 0xc7 memory memory system control sleep 0xbe pmc sleep mode control clkcon 0xc6 pmc clock control rfim 0x91 rf rf interrupt mask rfd 0xd9 rf rf data rfif 0xe9 rf rf interrupt flags rfst 0xe1 rf rf strobe commands worirq 0xa1 sleep timer sleep timer interrupts worctrl 0xa2 sleep timer sleep timer control worevt0 0xa3 sleep timer sleep timer event 0 timeout low byte worevt1 0xa5 sleep timer sleep ti mer event 0 timeout high byte wortime0 0xa4 sleep timer sleep timer low byte wortime1 0xa6 sleep timer sleep timer high byte t1cc0l 0xda timer1 timer 1 channel 0 capture/compare value low t1cc0h 0xdb timer1 timer 1 channel 0 capture/compare value high t1cc1l 0xdc timer1 timer 1 channel 1 capture/compare value low t1cc1h 0xdd timer1 timer 1 channel 1 capture/compare value high t1cc2l 0xde timer1 timer 1 channel 2 capture/compare value low t1cc2h 0xdf timer1 timer 1 channel 2 capture/compare value high t1cntl 0xe2 timer1 timer 1 counter low t1cnth 0xe3 timer1 timer 1 counter high t1ctl 0xe4 timer1 timer 1 control and status t1cctl0 0xe5 timer1 timer 1 channel 0 capture/compare control
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 42 of 252 register name sfr address module description t1cctl1 0xe6 timer1 timer 1 channel 1 capture/compare control t1cctl2 0xe7 timer1 timer 1 channel 2 capture/compare control t2ct 0x9c timer2 timer 2 timer count t2pr 0x9d timer2 timer 2 prescaler t2ctl 0x9e timer2 timer 2 control t3cnt 0xca timer3 timer 3 counter t3ctl 0xcb timer3 timer 3 control t3cctl0 0xcc timer3 timer 3 channel 0 capture/compare control t3cc0 0xcd timer3 timer 3 channel 0 capture/compare value t3cctl1 0xce timer3 timer 3 channel 1 capture/compare control t3cc1 0xcf timer3 timer 3 channel 1 capture/compare value t4cnt 0xea timer4 timer 4 counter t4ctl 0xeb timer4 timer 4 control t4cctl0 0xec timer4 timer 4 channel 0 capture/compare control t4cc0 0xed timer4 timer 4 channel 0 capture/compare value t4cctl1 0xee timer4 timer 4 channel 1 capture/compare control t4cc1 0xef timer4 timer 4 channel 1 capture/compare value timif 0xd8 tmint timers 1/3/4 joint interrupt mask/flags u0csr 0x86 usart0 usart 0 control and status u0dbuf 0xc1 usart0 usart 0 receive/transmit data buffer u0baud 0xc2 usart0 usart 0 baud rate control u0ucr 0xc4 usart0 usart 0 uart control u0gcr 0xc5 usart0 usart 0 generic control u1csr 0xf8 usart1 usart 1 control and status u1dbuf 0xf9 usart1 usart 1 receive/transmit data buffer u1baud 0xfa usart1 usart 1 baud rate control u1ucr 0xfb usart1 usart 1 uart control u1gcr 0xfc usart1 usart 1 generic control endian 0x95 memory usb endianess control ( cc2511fx ) wdctl 0xc9 wdt watchdog timer control 12.5 cpu registers this section describes the internal registers used by the cpu. 12.5.1 registers r0-r7 the CC2510FX/cc2511fx provides four register banks of eight registers each. these register banks are mapped in the data memory space at addresses 0x00-0x07, 0x08-0x0f, 0x10- 0x17 and 0x18-0x1f. each register bank contains the eight 8-bit register r0-r7 . the register bank to be used is selected through the program status word psw.rs[1:0] . 12.5.2 program status word
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 43 of 252 the program status word (psw) contains several bits that show the current state of the cpu. the program status word is accessible as an sfr and it is bit-addressable. psw contains the carry flag, auxiliary carry flag for bcd operations, register select bits, overflow flag and parity flag. two bits in psw are uncommitted and can be used as user-defined status flags . psw (0xd0) ? program status word bit name reset r/w description 7 cy 0 r/w carry flag. set to 1 when the last arithmetic operation resulted in a carry (during addition) or borro w (during subtraction), otherwise cleared to 0 by all arithmetic operations. 6 ac 0 r/w auxiliary carry flag for bcd operations. set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arithmetic operations. 5 f0 0 r/w user-defined, bit-addressable register bank select bits. select s which set of r7-r0 registers to use from four possible regi ster banks in data space. 00 bank 0, 0x00 ? 0x07 01 bank 1, 0x08 ? 0x0f 10 bank 2, 0x10 ? 0x17 4:3 rs[1:0] 00 r/w 11 bank 3, 0x18 ? 0x1f 2 ov 0 r/w overflow flag, set by arithmetic operations. set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide) . otherwise, the bit is cleared to 0 by all arithmetic operations. 1 f1 0 r/w user-defined, bit-addressable 0 p 0 r/w parity flag, parity of accumulator set by hardware to 1 if it contains an odd number of 1?s, otherwise it is cleared to 0 12.5.3 accumulator acc is the accumulator. this is the source and destination of most ar ithmetic instructions, data transfer and other instructions. the mnemonic for the accumu lator (in instructions involving the accumulator) refers to a instead of acc. acc (0xe0) ? accumulator bit name reset r/w description 7:0 acc[7:0] 0x00 r/w accumulator 12.5.4 b register the b register is used as the second 8-bit argument during execution of multiply and divide instructions. when not used for these purposes it may be used as a scratch-pad register to hold temporary data.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 44 of 252 b (0xf0) ? b register bit name reset r/w description 7:0 b[7:0] 0x00 r/w b register. used in mul/div instructions. 12.5.5 stack pointer the stack resides in data memory space and grows upwards. the push instruction first increments the stack pointer ( sp ) and then copies the byte into the stack. the stack pointer is initialized to 0x07 after a reset and it is incremented once to start from location 0x08, which is the first register ( r0 ) of the second register bank. thus, in order to use more than one register bank, the sp should be initialized to a different location not used for data storage. sp (0x81) ? stack pointer bit name reset r/w description 7:0 sp[7:0] 0x07 r/w stack pointer 12.6 instruction set summary the 8051 instruction set is summarized in
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 45 of 252 table 31. all mnemonics copyrighted ? intel corporation 1980. the following conventions are used in the instruction set summary: ? rn ? register r7-r0 of the currently selected register bank. ? direct ? 8-bit internal data location?s address. this can be data area (0x00 ? 0x7f) or sfr area (0x80 ? 0xff). ? @ri ? 8-bit internal data location, data area (0x00 ? 0xff) addressed indirectly through register r1 or r0. ? #data ? 8-bit constant included in instruction. ? #data16 ? 16-bit constant included in instruction. ? addr16 ? 16-bit desti nation address. used by lcall and ljmp . a valid branch can be anywhere within the 8/16/32 kb code program memory space. ? addr11 ? 11-bit desti nation address. used by acall and ajmp . the branch will be within the same 2 kb page of program memory as the first byte of the following instruction. ? rel ? signed (two?s complement) 8-bit offset byte. used by sjmp and all conditional jumps. range is ?128 to +127 bytes relative to firs t byte of the following instruction. ? bit ? direct addressed bit in data area or sfr. the instructions that affect cpu flag settings located in psw are listed in table 32 on page 49. note that operations on the psw or bits in psw will also affect the flag settings.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 46 of 252 table 31. instruction set summary mnemonic description hex opcode bytes cycles arithmetic operations add a,rn add register to accumulator 28-2f 1 1 add a,direct add direct byte to accumulator 25 2 2 add a,@ri add indirect ram to accumulator 26-27 1 2 add a,#data add immediate data to accumulator 24 2 2 addc a,rn add register to accumulator with carry flag 38-3f 1 1 addc a,direct add direct byte to a with carry flag 35 2 2 addc a,@ri add indirect ram to a with carry flag 36-37 1 2 addc a,#data add immediate data to a with carry flag 34 2 2 subb a,rn subtract register from a with borrow 98-9f 1 1 subb a,direct subtract direct byte from a with borrow 95 2 2 subb a,@ri subtract indirect ram from a with borrow 96-97 1 2 subb a,#data subtract immediate data from a with borrow 94 2 2 inc a increment accumulator 04 1 1 inc rn increment register 08-0f 1 2 inc direct increment direct byte 05 2 3 inc @ri increment indirect ram 06-07 1 3 inc dptr increment data pointer a3 1 1 dec a decrement accumulator 14 1 1 dec rn decrement register 18-1f 1 2 dec direct decrement direct byte 15 2 3 dec @ri decrement indirect ram 16-17 1 3 mul ab multiply a and b a4 1 5 div divide a by b 84 1 5 da a decimal adjust accumulator d4 1 1 logical operations anl a,rn and register to accumulator 58-5f 1 1 anl a,direct and direct byte to accumulator 55 2 2 anl a,@ri and indirect ram to accumulator 56-57 1 2 anl a,#data and immediate data to accumulator 54 2 2 anl direct,a and accumulator to direct byte 52 2 3 anl direct,#data and immediate data to direct byte 53 3 4 orl a,rn or register to accumulator 48-4f 1 1 orl a,direct or direct byte to accumulator 45 2 2 orl a,@ri or indirect ram to accumulator 46-47 1 2 orl a,#data or immediate data to accumulator 44 2 2 orl direct,a or accumulator to direct byte 42 2 3 orl direct,#data or immediate data to direct byte 43 3 4 xrl a,rn exclusive or register to accumulator 68-6f 1 1
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 47 of 252 mnemonic description hex opcode bytes cycles xrl a,direct exclusive or direct byte to accumulator 65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 66-67 1 2 xrl a,#data exclusive or immediate data to accumulator 64 2 2 xrl direct,a exclusive or accumu lator to direct byte 62 2 3 xrl direct,#data exclusive or imm ediate data to direct byte 63 3 4 clr a clear accumulator e4 1 1 cpl a complement accumulator f4 1 1 rl a rotate accumulator left 23 1 1 rlc a rotate accumulator left through carry 33 1 1 rr a rotate accumulator right 03 1 1 rrc a rotate accumulator right through carry 13 1 1 swap a swap nibbles within the accumulator c4 1 1 data transfers mov a,rn move register to accumulator e8-ef 1 1 mov a,direct move direct byte to accumulator e5 2 2 mov a,@ri move indirect ram to accumulator e6-e7 1 2 mov a,#data move immediate data to accumulator 74 2 2 mov rn,a move accumulator to register f8-ff 1 2 mov rn,direct move direct byte to register a8-af 2 4 mov rn,#data move immediate data to register 78-7f 2 2 mov direct,a move accumulator to direct byte f5 2 3 mov direct,rn move register to direct byte 88-8f 2 3 mov direct1,direct2 move direct byte to direct byte 85 3 4 mov direct,@ri move indirect ram to direct byte 86-87 2 4 mov direct,#data move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6-f7 1 3 mov @ri,direct move direct byte to indirect ram a6-a7 2 5 mov @ri,#data move immediate data to indirect ram 76-77 2 3 mov dptr,#data16 load data pointer with a 16-bit constant 90 3 3 movc a,@a+dptr move code byte relative to dptr to accumulator 93 1 3 movc a,@a+pc move code byte relative to pc to accumulator 83 1 3 movx a,@ri move external ram (8-bit address) to a e2-e3 1 3-10 movx a,@dptr move external ram (16- bit address) to a e0 1 3-10 movx @ri,a move a to external ram (8-bit address) f2-f3 1 4-11 movx @dptr,a move a to external ram (16-bit address) f0 1 4-11 push direct push direct byte onto stack c0 2 4 pop direct pop direct byte from stack d0 2 3 xch a,rn exchange register with accumulator c8-cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a,@ri exchange indirect ram with accumulator c6-c7 1 3 xchd a,@ri exchange low-order nibble indirect. ram with a d6-d7 1 3
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 48 of 252 mnemonic description hex opcode bytes cycles program branching acall addr11 absolute subroutine call xxx11 2 6 lcall addr16 long subroutine call 12 3 6 ret return from subroutine 22 1 4 reti return from interrupt 32 1 4 ajmp addr11 absolute jump xxx01 2 3 ljmp addr16 long jump 02 3 4 sjmp rel short jump (relative address) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 2 jz rel jump if accumulator is zero 60 2 3 jnz rel jump if accumulator is not zero 70 2 3 jc rel jump if carry flag is set 40 2 3 jnc jump if carry flag is not set 50 2 3 jb bit,rel jump if direct bit is set 20 3 4 jnb bit,rel jump if direct bit is not set 30 3 4 jbc bit,direct rel jump if direct bit is set and clear bit 10 3 4 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 4 cjne a,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immediate to reg. and jump if not equal b8-bf 3 4 cjne @ri,#data rel compare immediate to indire ct and jump if not equal b6-b7 3 4 djnz rn,rel decrement register and jump if not zero d8-df 2 3 djnz direct,rel decrement direct byte and jump if not zero d5 3 4 nop no operation 00 1 1 boolean variable operations clr c clear carry flag c3 1 1 clr bit clear direct bit c2 2 3 setb c set carry flag d3 1 1 setb bit set direct bit d2 2 3 cpl c complement carry flag b3 1 1 cpl bit complement direct bit b2 2 3 anl c,bit and direct bit to carry flag 82 2 2 anl c,/bit and complement of direct bit to carry b0 2 2 orl c,bit or direct bit to carry flag 72 2 2 orl c,/bit or complement of direct bit to carry a0 2 2 mov c,bit move direct bit to carry flag a2 2 2 mov bit,c move carry flag to direct bit 92 2 3
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 49 of 252 instruction cy ov ac add x x x addc x x x subb x x x mul 0 x div 0 x da x rrc x rlc x setb c 1 clr c x cpl c x anl c,bit x anl c,/bit x orl c,bit x orl c,/bit x mov c,bit x cjne x ?0?=set to 0, ?1?=set to 1, ?x?=set to 0/1, ?-?=not affected table 32: instructions that affect flag settings 12.7 interrupts the cpu has 18 interrupt sources. each source has its own request flag located in a set of interrupt flag sfr registers. each interrupt requested by the corresponding flag can be individually enabled or disabled. the definitions of the interrupt sources and the interrupt vectors are given in table 33. i2s and usart1 share interrupts. on the cc2511fx usb shares interrupt with port 2 inputs. the interrupt aliases for i2s and usb are listed in table 34. the original interrupt names, masks and flags in table 33, however, are used in the following sections. the interrupts are grouped into a set of priority level groups with select able priority levels. the interrupt enable registers are described in section 12.7.1 and the interrupt priority settings are described in section 12.7.4 on page 58. 12.7.1 interrupt masking each interrupt can be individually enabled or disabled by the interrupt enable bits in the interrupt enable sfrs ien0 , ien1 and ien2 . the interrupt enable sfrs are described below and summarized in table 33. note that some peripherals have several events that can generate the interrupt request associated with that peripheral. this applies to port 0, port 1, port 2, dma, timer 1, timer 3 , timer 4 and radio. these peripherals have interrupt mask bits for each internal interrupt source in the corresponding sfr registers. in order to use any of the interrupts in the CC2510FX/cc2511fx the following steps must be taken 1. set the corresponding individual interrupt enable bit in the ien0 , ien1 or ien2 register to 1. 2. set individual interrupt enable bit in the peripherals sfr register, if any. 3. begin the interrupt service routine at the corresponding ve ctor address of that interrupt. see table 33 for addresses. 4. enable global interrupt by setting the ea bit in ien0 to 1
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 50 of 252 12.7.2 interrupt vector sharing i2s shares rx and tx interrupt vectors with usart1 and the usb controller (on cc2511fx ) shares interrupt vector with port 2 inputs. see table 34 for addresses. interrupt number description interrupt name interrupt vector interrupt mask interrupt flag 0 rf tx done / rx ready rftxrx 03h ien0.rftxrxie tcon.rftxrxif 1 adc end of conversion adc 0bh ien0.adcie tcon.adcif 2 usart0 rx complete urx0 13h ien0.urx0ie tcon.urx0if 3 usart1 rx complete (i2s rx complete, see table 34) urx1 1bh ien0.urx1ie tcon.urx1if 4 aes encryption/decryption complete enc 23h ien0.encie s0con.encif 5 sleep timer compare st 2bh ien0.stie ircon.stif 6 port 2 inputs (also used for usb on cc2511fx, , see table 34) p2int 33h ien2.p2ie ircon2.p2if 7 usart0 tx complete utx0 3bh ien2.utx0ie ircon2.utx0if 8 dma transfer complete dma 43h ien1.dmaie ircon.dmaif 9 timer 1 (16-bit) capture/compare/overflow t1 4bh ien1.t1ie ircon.t1if 10 timer 2 (mac timer) overflow t2 53h ien1.t2ie ircon.t2if 11 timer 3 (8-bit) capture/compare/overflow t3 5bh ien1.t3ie ircon.t3if 12 timer 4 (8-bit) capture/compare/overflow t4 63h ien1.t4ie ircon.t4if 13 port 0 inputs (note: usb resume from suspend interrupt on p0_7 on cc2511fx ) p0int 6bh ien1.p0ie ircon.p0if 14 usart1 tx complete (i2s tx complete, see table 34) utx1 73h ien2.utx1ie ircon2.utx1if 15 port 1 inputs p1int 7bh ien2.p1ie ircon2.p1if 16 rf general interrupts rf 83h ien2.rfie s1con.rfif 17 watchdog overflow in timer mode wdt 8bh ien2.wdtie ircon2.wdtif table 33: interrupts overview interrupt number description interrupt name interrupt vector interrupt mask alias interrupt flag alias 3 i2s rx complete i2srx 1bh ien0.i2srxie tcon.i2srxif 14 i2s tx complete i2stx 73h ien2.i2stxie ircon2.i2stxif 6 usb interrupt pending ( cc2511fx ) usb 33h ien2.usbie ircon2.usbif table 34: shared interrupt vectors (i2s and usb)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 51 of 252 ien0 (0xa8) ? interrupt enable 0 register bit name reset r/w description disables all interrupts. 0 no interrupt will be acknowledged 7 ea 0 r/w 1 each interrupt source is indi vidually enabled or disabled by setting its corresponding enable bit 6 - 0 r0 not used. read as 0 stie ? sleep timer interrupt enable 0 interrupt disabled 5 stie 0 r/w 1 interrupt enabled encie ? aes encryption/decryption interrupt enable 0 interrupt disabled 4 encie 0 r/w 1 interrupt enabled urx1ie? usart1 rx interrupt enable / i2srxie ? i2s rx interrupt enable 0 interrupt disabled 3 urx1ie / i2srxie 0 r/w 1 interrupt enabled urx0ie - usart0 rx interrupt enable 0 interrupt disabled 2 urx0ie 0 r/w 1 interrupt enabled adcie ? adc interrupt enable 0 interrupt disabled 1 adcie 0 r/w 1 interrupt enabled rfrxtxie ? rf tx/rx done interrupt enable 0 interrupt disabled 0 rftxrxie 0 r/w 1 interrupt enabled
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 52 of 252 ien1 (0xb8) ? interrupt enable 1 register bit name reset r/w description 7:6 - 00 r0 not used. read as 0 p0ie ? port 0 interrupt enable 0 interrupt disabled 5 p0ie 0 r/w 1 interrupt enabled t4ie - timer 4 interrupt enable 0 interrupt disabled 4 t4ie 0 r/w 1 interrupt enabled t3ie - timer 3 interrupt enable 0 interrupt disabled 3 t3ie 0 r/w 1 interrupt enabled t2ie ? timer 2 interrupt enable 0 interrupt disabled 2 t2ie 0 r/w 1 interrupt enabled t1ie ? timer 1 interrupt enable 0 interrupt disabled 1 t1ie 0 r/w 1 interrupt enabled dmaie ? dma transfer interrupt enable 0 interrupt disabled 0 dmaie 0 r/w 1 interrupt enabled
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 53 of 252 ien2 (0x9a) ? interrupt enable 2 register bit name reset r/w description 7:6 - 00 r0 not used. read as 0 wdtie ? watchdog timer interrupt enable 0 interrupt disabled 5 wdtie 0 r/w 1 interrupt enabled p1ie ? port 1 interrupt enable 0 interrupt disabled 4 p1ie 0 r/w 1 interrupt enabled utx1ie ? usart1 tx interrupt enable / i2stxie ? i2s tx interrupt enable 0 interrupt disabled 3 utx1ie / i2stxie 0 r/w 1 interrupt enabled utx0ie - usart0 tx interrupt enable 0 interrupt disabled 2 utx0ie 0 r/w 1 interrupt enabled p2ie ? port 2 interrupt enable (also used for usb interrupt enable on cc2511fx ) 0 interrupt disabled 1 p2ie / usbie 0 r/w 1 interrupt enabled rfie ? rf general interrupt enable 0 interrupt disabled 0 rfie 0 r/w 1 interrupt enabled 12.7.3 interrupt processing when an interrupt occurs , the cpu will vector to the interrupt vector address as shown in table 33. once an interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a reti return from interrupt instruction. when a reti is performed, the cpu will return to the instruction that would have been next when the interrupt occurred. when the interrupt condition occurs, the cpu will also indicate this by setting an interrupt flag bit in the interrupt flag registers. this bit is set regardless of whether the interrupt is enabled or disabled. if the interrupt is enabled when an interrupt flag is set, then on the next instruction cycle th e interrupt will be acknowledged by hardware forcing an lcall to the appropriate vector address. interrupt response will require a varying amount of time depending on the state of the cpu when the interrupt occurs. if the cpu is performing an interrupt service with equal or greater priority, the new interrupt will be pending until it becomes the interrupt with highest priority. in other cases, the response time depends on current instruction. the fastest possible response to an interrupt is seven instruction cycles. this includes one instruction cycle for detecting the interrupt and six cycles to perform the lcall . clearing interrupt flags must be done correctly to ensure that no interrupts are lost, and no interrupt is proc essed more than once. the general rule is to first clear the mcu interrupt flag, and then clear any module flags. e.g. on the rf interrupt the mcu interrupt flag located in s1con.rfif is cleared first and
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 54 of 252 then the module interrupt flags located in the rfif register are cleared. one or more module flags can be cleared at once. however the safest approach is to only handle one interrupt source each time the interrupt is triggered, hence clearing only one module flag. when any module flag is cleared the chip will check if there are any module interrupt flags left that are both enabled and set, if so the mcu inte rrupt flag will be set and a new interrupt triggered. example code where only one module flag is handled and cleared each time the interrupt occurs: #pragma vector=rf_vector __interrupt void rf_interrupt (void) { s1con &= ~0x03; //clear mcu interrupt flag if(rfif & 0x80) //if tx underflow { ....handle tx underflow rfif = ~0x80; //clear module interrupt flag } else if(rfif & 0x40) //else if rx overflow { ....handle rx overflow rfif = ~0x40; //clear module interrupt flag } .....use ?else if? to check and handle other rfif flags } some interrupts are cleared by hardware when the cpu vectors the interrupt service routine, when handling these interrupts the mcu interrupt flag should not be cleared in software, only clear module interrupt flags. this applies to the following interrupts: ? rftxrx ? adc ? urx0 ? urx1/i2srx ? t1 ? t2 ? t3 ? t4
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 55 of 252 tcon (0x88) ? interrupt flag bit name reset r/w description urx1if ? usart1 rx interrupt flag. / i2srxif ? i2s rx interrupt flag. set to 1 when usart1 rx interrupt occurs and cleared when cpu vectors to the interrupt service routine. 0 interrupt not pending 7 urx1if / i2srxif 0 r/w h0 1 interrupt pending 6 - 0 r/w not used adcif ? adc interrupt flag. set to 1 when adc interrupt occurs and cleared when cpu vectors to the interrupt service routine. 0 interrupt not pending 5 adcif 0 r/w h0 1 interrupt pending 4 - 0 r/w not used urx0if ? usart0 rx interrupt flag. set to 1 when usart0 interrupt occurs and cleared when cpu vectors to the interrupt service routine. 0 interrupt not pending 3 urx0if 0 r/w h0 1 interrupt pending 2 it1 1 r/w reserved. must always be set to 1. rftxrxif ? rf tx/rx complete interrupt flag. set to 1 when rftxrx interrupt occurs and cleared when cpu vectors to the interrupt service routine. 0 interrupt not pending 1 rftxrxif 0 r/w h0 1 interrupt pending 0 it0 1 r/w reserved. must always be set to 1.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 56 of 252 s0con (0x98) ? interrupt flag 2 bit name reset r/w description 7:6 - 0 r/w not used encif ? aes interrupt. encif has two interrupt flags, encif_1 and encif_0. setting one of these flags will request interrupt service. both flags are set w hen the aes co-processor requests the interrupt. 0 interrupt not pending 1 encif_1 0 r/w 1 interrupt pending encif ? aes interrupt. encif has two interrupt flags, encif_1 and encif_0. setting one of these flags will request interrupt service. both flags are set w hen the aes co-processor requests the interrupt. 0 interrupt not pending 0 encif_0 0 r/w 1 interrupt pending s1con (0x9b) ? interrupt flag 3 bit name reset r/w description 7:6 - 0 r/w not used rfif ? rf general interrupt. rfif has two interrupt flags, rfif_1 and rfif_0. setting one of these flags will request interrupt service. both flags are set when th e radio requests the interrupt. 0 interrupt not pending 1 rfif_1 0 r/w 1 interrupt pending rfif ? rf general interrupt. rfif has two interrupt flags, rfif_1 and rfif_0. setting one of these flags will request interrupt service. both flags are set when th e radio requests the interrupt. 0 interrupt not pending 0 rfif_0 0 r/w 1 interrupt pending
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 57 of 252 ircon (0xc0) ? interrupt flag 4 bit name reset r/w description stif ? sleep timer interrupt flag 0 interrupt not pending 7 stif 0 r/w 1 interrupt pending 6 - 0 r/w not used p0if ? port 0 interrupt flag 0 interrupt not pending 5 p0if 0 r/w 1 interrupt pending t4if ? timer 4 interrupt flag. set to 1 when timer 4 interrupt occurs and cleared when cpu ve ctors to the interrupt service routine. 0 interrupt not pending 4 t4if 0 r/w h0 1 interrupt pending t3if ? timer 3 interrupt flag. set to 1 when timer 3 interrupt occurs and cleared when cpu ve ctors to the interrupt service routine. 0 interrupt not pending 3 t3if 0 r/w h0 1 interrupt pending t2if ? timer 2 interrupt flag. set to 1 when timer 2 interrupt occurs and cleared when cpu ve ctors to the interrupt service routine. 0 interrupt not pending 2 t2if 0 r/w h0 1 interrupt pending t1if ? timer 1 interrupt flag. set to 1 when timer 1 interrupt occurs and cleared when cpu ve ctors to the interrupt service routine. 0 interrupt not pending 1 t1if 0 r/w h0 1 interrupt pending dmaif ? dma complete interrupt flag. 0 interrupt not pending 0 dmaif 0 r/w 1 interrupt pending
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 58 of 252 ircon2 (0xe8) ? interrupt flag 5 bit name reset r/w description 7:5 - 00 r/w not used wdtif ? watchdog timer interrupt flag. 0 interrupt not pending 4 wdtif 0 r/w 1 interrupt pending p1if ? port 1 interrupt flag. 0 interrupt not pending 3 p1if 0 r/w 1 interrupt pending utx1if ? usart1 tx interrupt flag. / i2stxif ? i2s tx interrupt flag 0 interrupt not pending 2 utx1if / i2stxif 0 r/w 1 interrupt pending utx0if ? usart0 tx interrupt flag. 0 interrupt not pending 1 utx0if 0 r/w 1 interrupt pending p2if ? port2 interrupt flag. / usbif ? usb interrupt flag 0 interrupt not pending 0 p2if / usbif 0 r/w 1 interrupt pending 12.7.4 interrupt priority the interrupts are grouped into six interrupt priority groups and the priority for each group is set by the registers ip0 and ip1 . in order to assign a higher priority to an interrupt, i.e. to its interrupt group, the corresponding bits in ip0 and ip1 must be set as shown in table 35 on page 59. the interrupt priority groups with assigned interrupt sources are shown in table 36. each group is assigned one of four priority levels. while an interrupt service request is in progress, it cannot be interrupted by a lower or same level interrupt. in the case when interrupt requests of the same priority level are received simultaneously, the pollin g sequence shown in table 37 is used to resolve the priority of each request.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 59 of 252 ip1 (0xb9) ? interrupt priority 1 bit name reset r/w description 7:6 - 00 r/w not used. 5 ip1_5 0 r/w interrupt group 5, priority control bit 1, refer to table 35 4 ip1_4 0 r/w interrupt group 4, priority control bit 1, refer to table 35 3 ip1_3 0 r/w interrupt group 3, priority control bit 1, refer to table 35 2 ip1_2 0 r/w interrupt group 2, priority control bit 1, refer to table 35 1 ip1_1 0 r/w interrupt group 1, priority control bit 1, refer to table 35 0 ip1_0 0 r/w interrupt group 0, priority control bit 1, refer to table 35 ip0 (0xa9) ? interrupt priority 0 bit name reset r/w description 7:6 - 00 r/w not used. 5 ip0_5 0 r/w interrupt group 5, priority control bit 0, refer to table 35 4 ip0_4 0 r/w interrupt group 4, priority control bit 0, refer to table 35 3 ip0_3 0 r/w interrupt group 3, priority control bit 0, refer to table 35 2 ip0_2 0 r/w interrupt group 2, priority control bit 0, refer to table 35 1 ip0_1 0 r/w interrupt group 1, priority control bit 0, refer to table 35 0 ip0_0 0 r/w interrupt group 0, priority control bit 0, refer to table 35 ip1_x ip0_x priority level 0 0 0 ? lowest 0 1 1 1 0 2 1 1 3 ? highest table 35: priority level setting group interrupts ip0 rftxrx rf dma ip1 adc p2int / usb t1 ip2 urx0 utx0 t2 ip3 urx1 / i2s utx1 / i2s t3 ip4 enc p1int t4 ip5 st wdt p0int table 36: interrupt priority groups
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 60 of 252 interrupt number interrupt name 0 rftxrx 16 rf 8 dma 1 adc 9 t1 2 urx0 10 t2 3 urx1 / i2s 11 t3 4 enc 12 t4 5 st 13 p0int / (usb resume) 6 p2int / usb 7 utx0 14 utx1 / i2s 15 p1int 17 wdt polling sequence table 37: interrupt polling sequence 12.8 oscillators and clocks the CC2510FX/cc2511fx has one internal system clock. the source for the system clock can be either a 13 mhz high speed rc oscillator or a crystal oscillator. the crystal oscillator for CC2510FX operates at 26 mhz while the crystal oscillator for cc2511fx operates at 48 mhz. the 26 mhz clock is used directly as the system clock for CC2510FX . the 48 mhz clock is used by the usb controller only while a derived 24 mhz clock is used as the system clock. cloc k control is performed using the clkcon sfr register described in section 13.10. the choice of oscillato r allows a trade-off between high-accuracy in the case of the crystal oscillator and low power consumption when the high-frequency rc oscillator is used. note that operation of the rf transceiver and the usb requires that th e crystal oscillator is used. 12.9 debug interface the CC2510FX/cc2511fx includes a debug interface that provides a two-wire interface to an on-chip debug module. the debug interface allows programming the on-chip flash as well providing access to memory and register contents and debug features such as breakpoints, single-st epping and register modification. the debug interface uses the i/o pins p2_1 as debug data and p2_2 as debug clock during debug mode. these i/o pins can be used as general purpose i/o only while the device is not in debug mode. thus, the debug interface does not interfere with any peripheral i/o pins. debug mode is not supported in power modes 2 and 3 (pm2, pm3).
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 61 of 252 12.9.1 debug mode debug mode is entered by forcing two rising edge transitions on pin p2_2 (debug clock) while the reset_n input is held low. while in debug mode, pin p2_1 is the debug data bi-directional pin and p2_2 is the debug clock input pin. 12.9.2 debug communication the debug interface uses an spi-like two-wire interface consisting of the debug data (p2_1) and debug clock (p2_2) pins. data is driven on the bi-directional debug data pin at the positive edge of debug clock and data is sampled on the negative edge of this clock. debug commands are sent by an external host and consist of 1 to 4 output bytes (including command byte) from the host and an optional input byte read by the host. figure 11 shows a timing diagram of data on the debug interface. the first byte of the debug command is a command byte and is encoded as follows: ? bits 7 to 3 : instruction code ? bit 2 : return input byte to host when high ? bits 1 to 0 : number of output bytes from host following instruction code byte p2_2 p2_1 command first data byte second data byte host input byte figure 11: debug interface timing diagram 12.9.3 debug commands the debug commands are shown in table 38. some of the debug commands are described in further detail in the following sections 12.9.4 debug lock bit for software code security, the debug interface may be locked. when the debug lock bit , dbglock , is set (see section 13.16.3) all debug commands except chip_erase, read_status and get_chip_id are disabled and will not function. the chip_erase command is used to clear the debug lock bit. 12.9.5 debug configuration the commands wr_config and rd_config are used to access the debug configuration data byte. the format and description of this configuration data is shown in table 39. 12.9.6 debug status a debug status byte is read using the read_status command. the format and description of this debug status is shown in table 40. the read_status command is used e.g. for polling the status of flash chip erase after a chip_erase command or oscillator stable status required for debug commands halt, resume, debug_inst r, step_replace and step_instr.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 62 of 252 command instruction code description chip_erase 0001 0x00 perform flash chip erase (m ass erase) and clear lock bits. if any other command, except read_status, is issued, then the use of chip_erase is disabled. wr_config 0001 1x01 write configuration data. refer to table 39 rd_config 0010 0100 read configuration data. returns value set by wr_config command. get_pc 0010 1000 return value of 16-bit program counter. returns 2 bytes regardless of value of bit 2 in instruction code read_status 0011 0x00 read status byte. refer to table 40 set_hw_brkpnt 0011 1x11 set hardware breakpoint halt 0100 0100 halt cpu operation resume 0100 1100 resume cpu operation. the cpu must be in halted state for this command to be run. debug_instr 0101 01xx run debug instruction. the supplied instruction will be executed by the cpu without incrementing the program counter. the cpu must be in halted state for this command to be run. step_instr 0101 1100 step cpu instruction. the cpu will execute the next instruction from program memory and increment the program counter after execution. the cpu must be in halted state for this command to be run. step_replace 0110 01xx step and replace cpu instruction. the supplied instruction will be executed by the cpu instead of the next instruction in program memory. the program counter will be incremented after execution. the cpu must be in halted state for this command to be run. get_chip_id 0110 1000 return value of 16-bit ch ip id and version number. returns 2 bytes regardless of value of bit 2 of instruction code table 38: debug commands bit name description 7-4 - not used disable timers. di sable timer operation 0 do not disable timers 3 timers_off 1 disable timers dma pause 0 enable dma transfers 2 dma_pause 1 pause all dma transfers suspend timers. timer ope ration is suspended for debug instructions and if a step instruction is a branch. if not suspended these instructions would result in an extra timer count during the clock cycle in which the branch is executed 0 do not suspend timers 1 timer_suspend 1 suspend timers select flash information page in order to write flash lock bits. 0 select flash main page 0 sel_flash_info_page 1 select flash information page table 39: debug configuration
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 63 of 252 bit name description flash chip erase done 0 chip erase in progress 7 chip_erase_done 1 chip erase done pcon idle 0 cpu is running 6 pcon_idle 1 cpu is idle (clock gated) cpu halted 0 cpu running 5 cpu_halted 1 cpu halted power mode 0 0 power mode 1-3 selected 4 power_mode_0 1 power mode 0 selected halt status. returns cause of last cpu halt 0 cpu was halted by halt debug command 3 halt_status 1 cpu was halted by software or hardware breakpoint debug locked. returns value of dbglock bit 0 debug interface is not locked 2 debug_locked 1 debug interface is locked oscillators stable. this bi t represents the status of the clkcon.xsoc_stb and clkcon.hfrc_stb register bits. 0 oscillators not stable 1 oscillator_stable 1 oscillators stable stack overflow. this bit i ndicates when the cpu writes to data memory space at address 0xff which is possibly a stack overflow 0 no stack overflow 0 stack_overflow 1 stack overflow table 40: debug status 12.9.7 hardware breakpoints the debug command set_hw_brkpnt is used to set a hardware breakpoint. the CC2510FX/cc2511fx supports up to four hardware breakpoints. when a hardware breakpoint is enabled, it will compare the cpu address bus with the breakpoint.. when a match occurs, the cpu is halted. when issuing the set_hw_brkpnt, the external host must supply three data bytes that define the hardware breakpoint. the hardware breakpoint itself consists of 18 bits while three bits are used for control purposes. the format of the three data bytes for the set_hw_brkpnt command is as follows. the first data byte consists of the following: ? bits 7-5 : unused ? bits 4-3 : breakpoint number; 0-3 ? bit 2 : 1=enable, 0=disable ? bits 1-0 : memory bank bits. bits 17-16 of hardware breakpoint. the second data byte consists of bits 15-8 of the hardware breakpoint. the third data byte consists of bits 7-0 of the hardware breakpoint.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 64 of 252 12.9.8 flash programming programming of the on-chip flash is performed via the debug interface. the external host must initially send instructions using the debug_instr debug command to perform the flash programming with the flash controller as described in section 13.16. 12.10 ram the CC2510FX/cc2511fx contains static ram. at power-on the contents of ram is undefined. the ram size is 1, 2 or 4 kb in total, mapped to the memory range 0xf000 ? 0xffff. in the f8 and f16 versions parts of this memory range is not used. the memory locations 0xfda2-0xfeff consisting of 350 bytes in xdata memory that do not retain data when power modes pm2/3 is entered. all other ram memory locations are retained in all power modes. refer to table 28 for a description of the sram memory map. 12.11 flash memory the on-chip flash memory consists of 32768 bytes. the flash memory is primarily intended to hold program code. the flash memory has the following features: ? flash page erase time: 20 ms ? flash chip (mass) erase time: 20 ms ? flash write time (16 bit word): 20 s ? data retention 4 :100 years ? program/erase endurance: minimum 1,000 cycles the flash memory consists of the flash main page which is where the cpu reads program code and data. the flash memory also contains a flash information page which contains the flash lock bits. the flash information page and hence the lock bits is only accessed by first selecting this page through the debug interface. the flash controller (see section 13.16) is used to write and erase the contents of the flash memory. when the cpu reads instructions from flash memory, it fetches the next instruction through a cache. the instruction cache is provided mainly to reduce power consumption by reducing the amount of time the flash memory itself is accessed. the use of the instruction cache may be disabled with the memctr.cachdis register bit. 12.12 memory arbiter the CC2510FX/cc2511fx includes a memory arbiter which handles cpu and dma access to all memory space. a control register memctr is used to control the flash cache. the memctr register is described below. 4 at room temperature
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 65 of 252 memctr (0xc7) ? memory arbiter control bit name reset r/w description 7:6 - 00 r0 not used 5:4 - 01 r/w not used. must always be set to 01. 3:2 - 00 r0 not used flash cache disable. invalidates contents of instruction cache and forces all instruction read accesse s to read straight from flash memory. disabling will increase power consumption and is provided for debug purposes. 0 cache enabled 1 cachdis 0 r/w 1 cache disabled flash pre-fetch disabl e. disables pre-fetchi ng of cache read data. disabling will reduce perform ance and is provided for debug purposes. 0 flash pre-fetch enabled 0 prefdis 0 r/w 1 flash pre-fetch disabled
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 66 of 252 13 peripherals in the following sub-sections, each CC2510FX/cc2511fx peripheral is described in detail. the CC2510FX/cc2511fx has four timers. these timers all run on the tick frequency given by the power management controller register clkcon.tickspd . 13.1 i/o ports note: note: p0_6 and p0_7 does not exist on cc2511fx . the cc2511fx has 19 digital input/output pins available and the adc inputs 6 and 7 cannot be used. apart from this, all information in this section applies to both cc2511fx and CC2510FX . the CC2510FX has 21 digital input/output pins that can be configured as general purpose digital i/o or as peripheral i/o signals connected to the adc, timers, i2s or usart peripherals. the usage of the i/o ports is fully configurable from user software through a set of configuration registers. the i/o ports have the following key features: ? 21 digital input/output pins ? general purpose i/o or peripheral i/o ? pull-up or pull-down capability on inputs, except p1_0 and p1_1. ? external interrupt capability the external interrupt capability is available on all 21 i/o pins. thus, external devices may generate interrupts if required. the external interrupt feature can also be used to wake up from sleep modes. 13.1.1 general purpose i/o when used as general purpose i/o, the pins are organized as three 8-bit ports, ports 0-2, denoted p0, p1 and p2. p0 and p1 are complete 8-bit wide ports while p2 has only five usable bits (p2_0 to p2_4). all ports are both bit- and byte addressable through the sfr registers p0 , p1 and p2 . each port pin can individually be set to operate as a general purpose i/o or as a peripheral i/o. the output drive strength is 4 ma on all outputs, except for the tw o high-drive outputs, p1_0 and p1_1, which each have 20 ma output drive strength. to use a port as a general purpose i/o pin the pin must first be configured. the registers pxsel where x is the port number 0-2 are used to configure each pin in a port either as a general purpose i/o pin or as a peripheral i/o signal. by default, after a reset, all digital input/output pins are configured as general- purpose i/o pins. by default, all general-purpose i/o pins are configured as inputs. to change the direction of a port pin, at any time, the registers pxdir are used to set each port pin to be either an input or an output. thus by setting the appropriate bit within pxdir to 1, the corresponding pin becomes an output. when reading the port registers p0 , p1 and p2 , the logic values on the input pins are returned regardless of the pin configuration. this does not apply during the execution of read-modify-write inst ructions. the read- modify-write instructions when operating on a port registers are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an individual bit in a port register p0 , p1 or p2 . for these read-modify-write instructions, the value of the register, not the value on the pin, is read, modified, and written back to the port register. when used as an input, the general purpose i/o port pins can be configured to have a pull- up, pull-down or tri-state mode of operation. by default, after a reset, inputs are configured as inputs with pull-up. to deselect the pull- up/pull-down function on an input the appropriate bit within the pxinp must be set to 1. the i/o port pins p1_0 and p1_1 do not have pull-up/pull-down capability. in power modes pm1, pm2 and pm3 the i/o pins retain the i/o mode and output value (if applicable) that was set when pm1/2/3 was entered. 13.1.2 general purpose i/o interrupts general purpose i/o pins configured as inputs can be used to generate interrupts. the interrupts can be configured to trigger on either a rising or falling edge of the external signal. each of the p0 , p1 and p2 ports have separate interrupt enable bits common for all bits within the port located in the ien1-2 registers as follows:
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 67 of 252 ? ien1.p0ie : p0 interrupt enable ? ien2.p1ie : p1 interrupt enable ? ien2.p2ie : p2 interrupt enable in addition to these common interrupt enables, the bits within each port have interrupt enables located in i/o port sfr registers. each bit within p1 has an individual interrupt enable. in p0 the low-order nibble and the high-order nibble have their individual interrupt enables. for the p2_0 ? p2_4 inputs there is a common interrupt enable. when an interrupt condition occurs on one of the general purpose i/o pins, the corresponding interrupt status flag in the p0- p2 interrupt flag registers, p0ifg , p1ifg or p2ifg will be set to 1. the interrupt status flag is set regardless of whether the pin has its interrupt enable set. when an interrupt is serviced the interrupt stat us flag is cleared by writing a 0 to that flag. the sfr registers used for i/o interrupts are described in section 12.7 on page 49. the registers are summarized below: ? p1ien : p1 interrupt enables ? pictl : p0/p2 interrupt enables and p0-2 edge configuration ? p0ifg : p0 interrupt flags ? p1ifg : p1 interrupt flags ? p2ifg : p2 interrupt flags 13.1.3 general purpose i/o dma when used as general purpose i/o pins, the p0 and p1 ports are each associated with one dma trigger. these dma triggers are ioc_0 for p0 and ioc_1 for p1 as shown in table 42 on page 90. the ioc_0 or ioc_1 dma trigger is activated when an input transition occurs on one of the p0 or p1 pins respectively. note that only input transitions on pins configured as general purpose i/o inputs, will produce the dma trigger. 13.1.4 peripheral i/o this section describes how the digital input/output pins are configured as peripheral i/os. for each peripheral unit that can interface with an external system through the digital input/output pins, a description of how peripheral i/os are configured is given in the following sub-sections. in general, setting the appropriate pxsel bits to 1 is required to sele ct peripheral i/o function on a digital i/o pin. note that peripheral units have two alternative locations for their i/o pins, refer to table 41. the location to be used is selected by writing to percfg. it is possible to set percfg so that several peripherals are assigned to the same port pins. in such cases a set of peripheral priority control bits select the order of precedence between up to two peripherals at a time, when these are assigned to the same port pins.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 68 of 252 table 41: peripheral i/o pin mapping p0 p1 p2 periphery / function 7 1 6 1 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 adc a7 a6 a5 a4 a3 a2 a1 a0 c ss m0 mi usart0 alt 1 spi alt. 2 mo mi c ss tx rx usart0 alt. 1 uart alt. 2 tx rx mi m0 c ss usart1 alt.1 spi alt. 2 mi m0 c ss rx tx usart1 alt. 1 uart alt. 2 rx tx 2 1 0 timer1 alt.1 alt. 2 0 1 2 1 0 timer3 alt.1 alt. 2 1 0 1 0 timer4 alt.1 alt. 2 1 0 ck ws rx tx i2s alt. 1 alt. 2 ck ws rx tx 32.768khz xosc q2 q1 debug d c d d 1 this pin is only found on CC2510FX ,it does not exist on cc2511fx. 13.1.4.1 usart0 the sfr register bit percfg.u0cfg selects whether to use alternative 1 or alternative 2 locations. note that if both usarts are used, they must be on different ports, i.e. one on p0 and one on p1. this applies both in uart and spi mode. in table 41, the usart0 signals are shown as follows: uart: ? rx : rxdata ? tx : txdata spi: ? mi : miso ? mo : mosi ? c : sck ? ss : ssn p2dir.prip0 selects the order of precedence when assigning several peripherals to port 0, i.e. the situation when several peripherals are assigned to the same pin locations. when set to 00, usart0 has precedence. note that if uart mode is selected, usart1 or timer 1 will have precedence to use ports p0_4 and p0_5. p2sel.pri3p1 and p2sel.pri0p1 select the order of precedence when assigning several peripherals to port 1. usart0 has precedence when both are set to 0. note that if uart mode is selected, timer 1 or timer 3 will have precedence to use ports p1_2 and p1_3. 13.1.4.2 usart1 the sfr register bit percfg.u1cfg selects whether to use alternative 1 or alternative 2
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 69 of 252 locations. note that if both usarts are used, they must be on different ports, i.e. one on p0 and one on p1. this applies both in uart and spi mode. in table 41, the usart1 signals are shown as follows: ? rx : rxdata ? tx : txdata spi: ? mi : miso ? mo : mosi ? c : sck ? ss : ssn p2dir.prip0 selects the order of precedence when assigning several peripherals to port 0. when set to 01, usart1 has precedence. note that if uart mode is selected, usart0 or timer 1 will have precedence to use ports p0_2 and p0_3. p2sel.pri3p1 and p2sel.pri2p1 select the order of precedence when assigning several peripherals to port 1. usart1 has precedence when the former is set to 1 and the latter is set to 0. note that if uart mode is selected, usart0 or timer 3 will have precedence to use ports p2_4 and p2_5. 13.1.4.3 timer 1 percfg.t1cfg selects whether to use alternative 1 or alternative 2 locations. in table 41, the timer 1 signals are shown as the following: ? 0 : channel 0 capture/compare pin ? 1 : channel 1 capture/compare pin ? 2 : channel 2 capture/compare pin p2dir.prip0 selects the order of precedence when assigning several peripherals to port 0. when set to 10 or 11 the timer 1 channels have precedence. p2sel.pri1p1 and p2sel.pri0p1 select the order of precedence when assigning several peripherals to port 1. the timer 1 channels have precedence when the former is set low and the latter is set high. 13.1.4.4 timer 3 percfg.t3cfg selects whether to use alternative 1 or alternative 2 locations. in table 41, the timer 3 signals are shown as the following: ? 0 : channel 0 capture/compare pin ? 1 : channel 1 capture/compare pin p2sel.pri2p1 selects the order of precedence when assigning several peripherals to port 1. the timer 3 channels have precedence when the bit is set. 13.1.4.5 timer 4 percfg.t4cfg selects whether to use alternative 1 or alternative 2 locations. in table 41, the timer 4 signals are shown as the following: ? 0 : channel 0 capture/compare pin ? 1 : channel 1 capture/compare pin p2sel.pri1p1 selects the order of precedence when assigning several peripherals to port 1. the timer 4 channels have precedence when the bit is set. 13.1.4.6 i2s the i2s configuration register bit i2scfg1.ioloc selects whether to use alternative 1 or alternative 2 locations. in table 41, the i2s signals are shown as follows: ? ck : continous serial clock (sck) ? ws : word select ? rx : serial data in ? tx : serial data out 13.1.5 adc when using the adc in an application, the port 0 pins used must be configured as adc inputs. up to eight adc inputs can be used. the port pins are mapped to the adc inputs so that p0_7 ? p0_0 corresponds to ain7- ain0. to configure a port 0 pin to be used as an adc input the corresponding bit in the adccfg register must be set to 1. the default values in this register select the port 0 pins as non-adc input i.e. digital input/outputs. the settings in the adccfg register override the settings in p0sel .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 70 of 252 the adc can be configured to use the general-purpose i/o pin p2_0 as an external trigger to start conversions. p2_0 must be configured as a general-purpose i/o in input mode, when being used for adc external trigger. refer to section 13.7 on page 127 for a detailed description of use of the adc. 13.1.6 debug interface port pins p2_1 and p2_2 are used for debug data and clock signals, respectively. these are shown as dd (debug data) and dc (debug clock) in table 41. when the debug interface is in use, p2dir should select these pins as inputs. the state of p2sel is overridden by the debug interface. also, the direction is overridden when the chip changes the direction to supply the external host with data. 13.1.7 32.768 khz xosc input ports p2_3 and p2_4 are used to connect an external 32.768 khz crystal. these port pins will be used by the 32.768 khz crystal oscillator when clkcon.osc32k is low, regardless of register settings. the port pins will be set in analog mode when clkcon.osc32k is low. 13.1.8 unused i/o pins unused i/o pins should have a defined level and not be left floating. one way to do this is to leave the pin unconnected and configure the pin as a general purpose i/o input with pull-up resistor. this is also the state of all pins during reset (except p1_0 and p1_1 which do not have pull-up/pull-down resi stors). alternatively the pin can be configured as a general purpose i/o output. in both cases the pin should not be connected directly to vdd or gnd in order to avoid excessive power consumption. 13.1.9 ioc registers the registers for the io ports are described in this section. the registers are: ? p0 port 0 ? p1 port 1 ? p2 port 2 ? percfg peripheral control register ? adccfg adc input configuration register ? p0sel port 0 function select register ? p1sel port 1 function select register ? p2sel port 2 function select register ? p0dir port 0 direction register ? p1dir port 1 direction register ? p2dir port 2 direction register ? p0inp port 0 input mode register ? p1inp port 1 input mode register ? p2inp port 2 input mode register ? p0ifg port 0 interrupt status flag register ? p1ifg port 1 interrupt status flag register ? p2ifg port 2 interrupt status flag register ? pictl interrupt mask and edge register ? p1ien port 1 interrupt mask register
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 71 of 252 p0 (0x80) ? port 0 bit name reset r/w description 7:0 p0[7:0] 0xff r/w port 0. general purpose i/o port. bit-addressable. p1 (0x90) ? port 1 bit name reset r/w description 7:0 p1[7:0] 0xff r/w port 1. general purpose i/o port. bit-addressable. p2 (0xa0) ? port 2 bit name reset r/w description 7:0 - 000 r0 not used 4:0 p2[4:0] 0x1f r/w port 2. general purpose i/o port. bit-addressable. percfg (0xf1) ? peripheral control bit name reset r/w description 7 - 0 r0 not used timer 1 i/o location 0 alternative 1 location 6 t1cfg 0 r/w 1 alternative 2 location timer 3 i/o location 0 alternative 1 location 5 t3cfg 0 r/w 1 alternative 2 location timer 4 i/o location 0 alternative 1 location 4 t4cfg 0 r/w 1 alternative 2 location 3:2 - 00 r0 not used usart1 i/o location 0 alternative 1 location 1 u1cfg 0 r/w 1 alternative 2 location usart0 i/o location 0 alternative 1 location 0 u0cfg 0 r/w 1 alternative 2 location
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 72 of 252 adccfg (0xf2) ? adc input configuration bit name reset r/w description adc input configuration. adccfg[7:0] shall select p0_7 - p0_0 as adc inputs ain7 ? ain0 0 adc input disabled 7:0 adccfg[7:0] 0x00 r/w 1 adc input enabled p0sel (0xf3) ? port 0 function select bit name reset r/w description p0_7 function select 0 general purpose i/o 7 selp0_7 0 r/w 1 peripheral function p0_6 function select 0 general purpose i/o 6 selp0_6 0 r/w 1 peripheral function p0_5 function select 0 general purpose i/o 5 selp0_5 0 r/w 1 peripheral function p0_4 function select 0 general purpose i/o 4 selp0_4 0 r/w 1 peripheral function p0_3 function select 0 general purpose i/o 3 selp0_3 0 r/w 1 peripheral function p0_2 function select 0 general purpose i/o 2 selp0_2 0 r/w 1 peripheral function p0_1 function select 0 general purpose i/o 1 selp0_1 0 r/w 1 peripheral function p0_0 function select 0 general purpose i/o 0 selp0_0 0 r/w 1 peripheral function
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 73 of 252 p1sel (0xf4) ? port 1 function select bit name reset r/w description p1_7 function select 0 general purpose i/o 7 selp1_7 0 r/w 1 peripheral function p1_6 function select 0 general purpose i/o 6 selp1_6 0 r/w 1 peripheral function p1_5 function select 0 general purpose i/o 5 selp1_5 0 r/w 1 peripheral function p1_4 function select 0 general purpose i/o 4 selp1_4 0 r/w 1 peripheral function p1_3 function select 0 general purpose i/o 3 selp1_3 0 r/w 1 peripheral function p1_2 function select 0 general purpose i/o 2 selp1_2 0 r/w 1 peripheral function p1_1 function select 0 general purpose i/o 1 selp1_1 0 r/w 1 peripheral function p1_0 function select 0 general purpose i/o 0 selp1_0 0 r/w 1 peripheral function
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 74 of 252 p2sel (0xf5) ? port 2 function select bit name reset r/w description 7 - 0 r0 not used port 1 peripheral priority contr ol. these bits shall determine the order of priority in the case when percfg assigns usart0 and usart1 to the same pins. 0 usart0 has priority 6 pri3p1 0 r/w 1 usart1 has priority port 1 peripheral priority contr ol. these bits shall determine the order of priority in the case when percfg assigns usart1 and timer 3 to the same pins. 0 usart1 has priority 5 pri2p1 0 r/w 1 timer 3 has priority port 1 peripheral priority contr ol. these bits shall determine the order of priority in the case when percfg assigns timer 1 and timer 4 to the same pins. 0 timer 1 has priority 4 pri1p1 0 r/w 1 timer 4 has priority port 1 peripheral priority contr ol. these bits shall determine the order of priority in the case when percfg assigns usart0 and timer 1 to the same pins. 0 usart0 has priority 3 pri0p1 0 r/w 1 timer 1 has priority p2_4 function select 0 general purpose i/o 2 selp2_4 0 r/w 1 peripheral function p2_3 function select 0 general purpose i/o 1 selp2_3 0 r/w 1 peripheral function p2_0 function select 0 general purpose i/o 0 selp2_0 0 r/w 1 peripheral function
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 75 of 252 p0dir (0xfd) ? port 0 direction bit name reset r/w description p0_7 i/o direction 0 input 7 dirp0_7 0 r/w 1 output p0_6 i/o direction 0 input 6 dirp0_6 0 r/w 1 output p0_5 i/o direction 0 input 5 dirp0_5 0 r/w 1 output p0_4 i/o direction 0 input 4 dirp0_4 0 r/w 1 output p0_3 i/o direction 0 input 3 dirp0_3 0 r/w 1 output p0_2 i/o direction 0 input 2 dirp0_2 0 r/w 1 output p0_1 i/o direction 0 input 1 dirp0_1 0 r/w 1 output p0_0 i/o direction 0 input 0 dirp0_0 0 r/w 1 output
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 76 of 252 p1dir (0xfe) ? port 1 direction bit name reset r/w description p1_7 i/o direction 0 input 7 dirp1_7 0 r/w 1 output p1_6 i/o direction 0 input 6 dirp1_6 0 r/w 1 output p1_5 i/o direction 0 input 5 dirp1_5 0 r/w 1 output p1_4 i/o direction 0 input 4 dirp1_4 0 r/w 1 output p1_3 i/o direction 0 input 3 dirp1_3 0 r/w 1 output p1_2 i/o direction 0 input 2 dirp1_2 0 r/w 1 output p1_1 i/o direction 0 input 1 dirp1_1 0 r/w 1 output p1_0 i/o direction 0 input 0 dirp1_0 0 r/w 1 output
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 77 of 252 p2dir (0xff) ? port 2 direction bit name reset r/w description port 0 peripheral priority contr ol. these bits shall determine the order of priority in the case when percfg assigns several peripherals to the same pins 00 usart0 ? usart1 01 usart1 ? usart0 10 timer 1 channels 0 and 1 ? usart1 7:6 prip0[1:0] 0 r/w 11 timer 1 channel 2 ? usart0 5 - 0 r0 not used p2_4 i/o direction 0 input 4 dirp2_4 0 r/w 1 output p2_3 i/o direction 0 input 3 dirp2_3 0 r/w 1 output p2_2 i/o direction 0 input 2 dirp2_2 0 r/w 1 output p2_1 i/o direction 0 input 1 dirp2_1 0 r/w 1 output p2_0 i/o direction 0 input 0 dirp2_0 0 r/w 1 output
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 78 of 252 p0inp (0x8f) ? port 0 input mode bit name reset r/w description p0_7 i/o input mode 0 pull-up / pull-down 7 mdp0_7 0 r/w 1 tristate p0_6 i/o input mode 0 pull-up / pull-down 6 mdp0_6 0 r/w 1 tristate p0_5 i/o input mode 0 pull-up / pull-down 5 mdp0_5 0 r/w 1 tristate p0_4 i/o input mode 0 pull-up / pull-down 4 mdp0_4 0 r/w 1 tristate p0_3 i/o input mode 0 pull-up / pull-down 3 mdp0_3 0 r/w 1 tristate p0_2 i/o input mode 0 pull-up / pull-down 2 mdp0_2 0 r/w 1 tristate p0_1 i/o input mode 0 pull-up / pull-down 1 mdp0_1 0 r/w 1 tristate p0_0 i/o input mode 0 pull-up / pull-down 0 mdp0_0 0 r/w 1 tristate
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 79 of 252 p1inp (0xf6) ? port 1 input mode bit name reset r/w description p1_7 i/o input mode 0 pull-up / pull-down 7 mdp1_7 0 r/w 1 tristate p1_6 i/o input mode 0 pull-up / pull-down 6 mdp1_6 0 r/w 1 tristate p1_5 i/o input mode 0 pull-up / pull-down 5 mdp1_5 0 r/w 1 tristate p1_4 i/o input mode 0 pull-up / pull-down 4 mdp1_4 0 r/w 1 tristate p1_3 i/o input mode 0 pull-up / pull-down 3 mdp1_3 0 r/w 1 tristate p1_2 i/o input mode 0 pull-up / pull-down 2 mdp1_2 0 r/w 1 tristate 1:0 - 00 r0 not used
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 80 of 252 p2inp (0xf7) ? port 2 input mode bit name reset r/w description port 2 pull-up/down select. selects function for all port 2 pins configured as pull-up/pull-down inputs. 0 pull-up 7 pdup2 0 r/w 1 pull-down port 1 pull-up/down select. selects function for all port 1 pins configured as pull-up/pull-down inputs. 0 pull-up 6 pdup1 0 r/w 1 pull-down port 0 pull-up/down select. selects function for all port 0 pins configured as pull-up/pull-down inputs. 0 pull-up 5 pdup0 0 r/w 1 pull-down p2_4 i/o input mode 0 pull-up / pull-down 4 mdp2_4 0 r/w 1 tristate p2_3 i/o input mode 0 pull-up / pull-down 3 mdp2_3 0 r/w 1 tristate p2_2 i/o input mode 0 pull-up / pull-down 2 mdp2_2 0 r/w 1 tristate p2_1 i/o input mode 0 pull-up / pull-down 1 mdp2_1 0 r/w 1 tristate p2_0 i/o input mode 0 pull-up / pull-down 0 mdp2_0 0 r/w 1 tristate
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 81 of 252 p0ifg (0x89) ? port 0 interrupt status flag CC2510FX : bit name reset r/w description 7:0 p0if[7:0] 0x00 r/w0 port 0, inputs 7 to 0 inte rrupt status flags. when an input port pin has an interrupt request pending, t he corresponding flag bit will be set. cc2511fx : bit name reset r/w description 7 usb_resume 0 r/w0 usb resume detected during suspend. 6 - 0 r0 not used 5:0 p0if[5:0] 0x00 r/w0 port 0, inputs 7 to 0 inte rrupt status flags. when an input port pin has an interrupt request pending, t he corresponding flag bit will be set. p1ifg (0x8a) ? port 1 interrupt status flag bit name reset r/w description 7:0 p1if[7:0] 0x00 r/w0 port 1, inputs 7 to 0 inte rrupt status flags. when an input port pin has an interrupt request pending, t he corresponding flag bit will be set. p2ifg (0x8b) ? port 2 interrupt status flag bit name reset r/w description 7:5 - 000 r0 not used. 4:0 p2if[4:0] 0x00 r/w0 port 2, inputs 4 to 0 inte rrupt status flags. when an input port pin has an interrupt request pending, t he corresponding flag bit will be set.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 82 of 252 pictl (0x8c) ? port interrupt control bit name reset r/w description 7 - 0 r0 not used 6 - 0 r/w reserved. write 0 port 2, inputs 4 to 0 interrupt enable. this bit enables interrupt requests for the port 2 inputs 4 to 0. 0 interrupts are disabled 5 p2ien 0 r/w 1 interrupts are enabled port 0, inputs 7 to 4 interrupt enable. this bit enables interrupt requests for the port 0 inputs 7 to 4. 0 interrupts are disabled 4 p0ienh 0 r/w 1 interrupts are enabled port 0, inputs 3 to 0 interrupt enable. this bit enables interrupt requests for the port 0 inputs 3 to 0. 0 interrupts are disabled 3 p0ienl 0 r/w 1 interrupts are enabled port 2, inputs 4 to 0 interrupt configuration. this bit selects the interrupt request condition for all port 2 inputs 0 rising edge on input gives interrupt 2 p2icon 0 r/w 1 falling edge on input gives interrupt port 1, inputs 7 to 0 interrupt configuration. this bit selects the interrupt request condition for all port 1 inputs 0 rising edge on input gives interrupt 1 p1icon 0 r/w 1 falling edge on input gives interrupt port 0, inputs 7 to 0 interrupt configuration. this bit selects the interrupt request condition for all port 0 inputs. for cc2511fx this bit must not be set to 1 when usb is used, since the internal usb resume interrupt mapped to p0[7] uses rising edge. 0 rising edge on input gives interrupt 0 p0icon 0 r/w 1 falling edge on input gives interrupt
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 83 of 252 p1ien (0x8d) ? port 1 interrupt mask bit name reset r/w description port p1_7 interrupt enable 0 interrupts are disabled 7 p1_7ien 0 r/w 1 interrupts are enabled port p1_6 interrupt enable 0 interrupts are disabled 6 p1_6ien 0 r/w 1 interrupts are enabled port p1_5 interrupt enable 0 interrupts are disabled 5 p1_5ien 0 r/w 1 interrupts are enabled port p1_4 interrupt enable 0 interrupts are disabled 4 p1_4ien 0 r/w 1 interrupts are enabled port p1_3 interrupt enable 0 interrupts are disabled 3 p1_3ien 0 r/w 1 interrupts are enabled port p1_2 interrupt enable 0 interrupts are disabled 2 p1_2ien 0 r/w 1 interrupts are enabled port p1_1 interrupt enable 0 interrupts are disabled 1 p1_1ien 0 r/w 1 interrupts are enabled port p1_0 interrupt enable 0 interrupts are disabled 0 p1_0ien 0 r/w 1 interrupts are enabled
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 84 of 252 13.2 dma controller the CC2510FX/cc2511fx includes a direct memory access (dma) controller, which can be used to relieve the 8051 cpu core of handling data movement operations. thus the CC2510FX/cc2511fx can achieve high overall performance with good power efficiency. the dma controller can move data from a peripheral unit such as adc or rf transceiver to memory with mini mum cpu intervention. the dma controller module coordinates all dma transfers, ensuring that dma requests are prioritized appropriately relative to each other and cpu memory access. the dma controller contains a number of programmable dma channels for memory-to-memory data movement. the dma controller controls data movement over the entire xdata memory space. since all the sfr registers (except some internal registers) are mapped into the dma memory space these flexible dma channels can be used to unburden the 8051 in innovative ways, e.g. feed a usart and i2s with data from memory, periodically transfer samples between adc and memory, transfer data to and from usb fifos ( cc2511fx ) etc. use of the dma can also reduce system power consumption by letting the cpu run on a lower frequency ( clkcon.clkspd ) . the main features of the dma controller are as follows: ? five independent dma channels ? three configurable levels of dma channel priority ? 30 configurable transfer trigger events ? independent control of source and destination address ? single, block and repeated transfer modes ? supports variable transfer length by including the length field in the transfer data ? can operate in either word-size or byte-size mode 13.2.1 dma operation there are five dma channels available in the dma controller numbered channel 0 to channel 4. each dma channel can move data from one place within the dma memory space to another. in order to use a dma channel it must first be configured as described in sections 13.2.2 and 13.2.3. once a dma channel has been configured it must be armed before any transfers are allowed to be initiated. a dma channel is armed by setting the appropriate bit in the dma channel arm register dmaarm . when a dma channel is armed a transfer will begin when the configured dma trigger event occurs. there are 30 possible dma trigger events, e.g. uart trans fer, timer overflow etc. the trigger event to be used by a dma channel is set by the dma channel configuration. the dma trigger events are listed in table 42. in addition to starting a dma transfer through the dma trigger events, the user software may force a dma transfer to begin by setting the corresponding dmareq bit. figure 12 shows the dma state diagram.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 85 of 252 figure 12: dma operation 13.2.2 dma configuration parameters setup and control of the dma operation is performed by the user software. this section describes the parameters that must be configured before a dma channel can be used. section 13.2.3 on page 88 describes
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 86 of 252 how the parameters are set up in software and passed to the dma controller. the behavior of each of the five dma channels is configured with the following parameters: source address . the first address from which the dma channel should read data. destination address . the first address to which the dma channel should write the data read from the source address. the user must ensure that the destination is writable. transfer count . the number of transfers to perform before rearming or disarming the dma channel and alerting the cpu with an interrupt request. the length can be defined in the configuration or it can be defined as described next as vlen setting. vlen setting. the dma channel is capable of variable length transfers using the first byte or word at the source addr ess to set the transfer length. when doing this, various options regarding how to count number of bytes to transfer are available. priority . the priority of the dma transfers for the dma channel in respect to the cpu and other dma channels and access ports. trigger event . all dma transfers are initiated by so-called dma trigger events. this trigger either starts a dma block transfer or a single dma transfer. source and destination increment. the source and destination addresses can be controlled to increment, decrement, or not change, in order to give good flexibility for various types of transfers. transfer mode. the transfer mode determines whether the transfer should be a single transfer or a block transfer, or repeated versions of these. byte or word transfers. determines whether each dma transfer should be 8-bit (byte) or 16-bit (word). interrupt mask. an interrupt request is generated upon completion of the dma transfer. the interrupt mask bit controls if the interrupt generation is enabled or disabled. m8: decide whether to use seven or eight bits of length byte for transfer length. only applicable when doing byte transfers. a detailed description of the configuration parameters is given in the following sections. 13.2.2.1 source address the address of the location in xdata memory space where the dma channel shall start to read data for the transfer. 13.2.2.2 destination address the address of the location in xdata memory space where the dma channel shall start to write transfer data. the user must ensure that the destination is writable. 13.2.2.3 transfer count the number of bytes/words needed to be transferred for the dma transfer to be complete. when the transfer count is reached, the dma controller rearms or disarms the dma channel (depending on transfer mode) and alerts the cpu with an interrupt request. the transfer count can be defined in the configuration or it can be defined as a variable length described in the next section. 13.2.2.4 vlen setting the dma channel is capable of using the first byte or word (for word, bits 12:0 are used) in source data as the transfer length. this allows variable length transfers. when using variable length transfer, various options regarding how to count number of bytes to transfer is given. in any case, the len setting is used as maximum transfer count. no te that the m8 bit is only used when byte size transfers are chosen. options are: 1. default : transfer number of bytes/words commanded by first byte/word + 1 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word) 2. transfer number of bytes/words commanded by first byte/word 3. transfer number of bytes/words commanded by first byte/word + 2 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 1) 4. transfer number of bytes/words commanded by first byte/word + 3 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 2)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 87 of 252 length=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n length=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n length=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n length=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n byte/word n+1 byte/word n+1 byte/word n+2 vlen=001 vlen=010 vlen=011 vlen=100 figure 13: variable length (vlen) transfer options 13.2.2.5 trigger event each dma channel can be set up to sense on a single trigger. this field determines which trigger the dma channel shall sense. in addition to the configured trigger, a dma channel can always be triggered by setting its designated dmareq.dmareqx flag. the dma trigger sources are described in table 42 on page 90. 13.2.2.6 source and destination increment when the dma channel is armed or rearmed the source and destination addresses are transferred to internal address pointers. the possibilities for addre ss increment are : ? increment by zero. the address pointer shall remain fixed after each transfer. ? increment by one. the address pointer shall increment one count after each transfer. ? increment by two. the address pointer shall increment two counts after each transfer. ? decrement by one. the address pointer shall decrement one count after each transfer. 13.2.2.7 dma transfer mode the transfer mode determines how the dma channel behaves when it starts transferring data. there are four transfer modes described below: single . on a trigger a single dma transfer occurs and the dma channel awaits the next trigger. after the number of transfers specified by the transfer count are completed, the cpu is notified and the dma channel is disarmed. block . on a trigger the number of dma transfers specified by the transfer count is performed as quickly as possible, after which the cpu is notified and the dma channel is disarmed. repeated single. on a trigger a single dma transfer occurs and the dma channel awaits the next trigger. after the number of transfers specified by the transfer count are completed, the cpu is notified and the dma channel is rearmed. repeated block. on a trigger the number of dma transfers specified by the transfer count is performed as quickly as possible, after which the cpu is notified and the dma channel is rearmed. 13.2.2.8 dma priority a dma priority is associated with each dma channel. the dma priority is used to determine the winner in the case of multiple
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 88 of 252 simultaneous internal memory requests, and whether the dma memory access should have priority or not over a simultaneous cpu memory access. in case of an internal tie, a round-robin scheme is used to ensure access for all. there are three levels of dma priority: high . highest internal priority. dma access will always prevail over cpu access. normal . second highest internal priority. guarantees that dma ac cess prevails over cpu on at least every second try. low . lowest internal priority. dma access will always defer to a cpu access. 13.2.2.9 byte or word transfers determines whether 8-bit (byte) or 16-bit (word) are done. 13.2.2.10 interrupt mask upon completing a dma transfer, the channel can generate an interrupt to the processor. this bit will mask the interrupt. 13.2.2.11 mode 8 setting this field determines whether to use seven or 8 bits of length byte for transfer length. only applicable when doing byte transfers. 13.2.3 dma configuration setup the dma channel parameters such as address mode, transfer mode and priority described in the previous section have to be configured before a dma channel can be armed and activated. the parameters are not configured directly through sfr registers, but instead they are written in a special dma configuration data structure in memory. each dma channel in use requires its own dma configuration data structure. the dma configuration data structure consists of eight bytes and is described in section 13.2.6 a dma configuration data structure may reside at any location in xdata decided upon by the user software, and t he address location is passed to the dma controller through a set of sfrs dmaxcfgh:dmaxcfgl , once a channel has been armed, the dm a controller will read the configuration data structure for that channel, given by the address in dmaxcfgh:dmaxcfgl . it is important to note that the method for specifying the start address for the dma configuration data structure differs between dma channel 0 and dma channels 1-4 as follows: dma0cfgh:dma0cfgl gives the start address for dma channel 0 configuration data structure. dma1cfgh:dma1cfgl gives the start address for dma channel 1 configuration data structure followed by channel 2-4 configuration data structures. thus the dma controller expects the dma configuration data structures for dma channels 1-4 to lie in a contiguous area in memory, starting at the address held in dma1cfgh:dma1cfgl and consisting of 32 bytes. 13.2.4 stopping dma transfers ongoing dma transfer or armed dma channels will be aborted using the dmaarm register to disarm the dma channel. one or more dma channels are aborted by writing the following to the dmaarm register. ? writing a 1 to dmaarm.abort, and at the same time, ? select which dma channels to abort by setting the corresponding, dmaarm.dmaarmx bits. an example of dma channel arm and disarm is shown in figure 14. mov dmaarm, #0x03 ; arm dma channel 0 and 1 mov dmaarm, #0x81 ; disarm dma channel 0, ; channel 1 is still armed figure 14: dma arm/disarm example
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 89 of 252 13.2.5 dma interrupts each dma channel can be configured to generate an interrupt to the cpu upon completing a dma transfer. this is accomplished with the irqmask bit in the channel configuration. the corresponding interrupt flag in the dmairq sfr register will be set when the interrupt is generated. regardless of the irqmask bit in the channel configuration, the interrupt flag will be set upon dma channel complete. thus software should always check (and clear) this register when rearming a channel with a changed irqmask setting. failure to do so could generate an interrupt based on the stored interrupt flag. 13.2.6 dma configuration data structure for each dma channel, the dma configuration data structure consists of eight bytes. the configuration data structure is described in table 43. 13.2.7 dma usb endianess ( cc2511fx ) when a usb fifo is accessed using word transfer dma the endianess of the word read/written can be controlled by setting the endian.usbwle and endian.usbrle configuration bits in the endian register. see section 13.15 for details.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 90 of 252 dma trigger number dma trigger name functional unit description 0 none dma no trigger, setting dmareq.dmareqx bit starts transfer 1 prev dma dma channel is triggered by co mpletion of previous channel 2 t1_ch0 timer 1 timer 1, compare, channel 0 3 t1_ch1 timer 1 timer 1, compare, channel 1 4 t1_ch2 timer 1 timer 1, compare, channel 2 5 - - not in use. 6 t2_ovfl timer 2 timer 2, overflow 7 t3_ch0 timer 3 timer 3, compare, channel 0 8 t3_ch1 timer 3 timer 3, compare, channel 1 9 t4_ch0 timer 4 timer 4, compare, channel 0 10 t4_ch1 timer 4 timer 4, compare, channel 1 11 st sleep timer sleep timer compare 12 ioc_0 io controller io pin input transition 13 ioc_1 io controller io pin input transition 14 urx0 usart0 usart0 rx complete 15 utx0 usart0 usart0 tx complete 16 urx1 usart1 usart1 rx complete 17 utx1 usart1 usart1 tx complete 18 flash flash controller flash data write complete 19 radio radio rf packet byte received/transmit 20 adc_chall adc adc end of a conversion in a sequence, sample ready 21 adc_ch0 adc adc end of conversion channel 0 in sequence, sample ready 22 adc_ch1 adc adc end of conversion channel 1 in sequence, sample ready 23 adc_ch2 adc adc end of conversion channel 2 in sequence, sample ready 24 adc_ch3 adc adc end of conversion channel 3 in sequence, sample ready 25 adc_ch4 adc adc end of conversion channel 4 in sequence, sample ready 26 adc_ch5 adc adc end of conversion channel 5 in sequence, sample ready adc_ch6 adc adc end of conversion channel 6 in sequence, sample ready 27 i2srx i2s i2s rx complete adc_ch7 adc adc end of conversion channel 7 in sequence, sample ready 28 i2stx i2s i2s tx complete 29 enc_dw aes aes encryption processor requests download input data 30 enc_up aes aes encryption processor requests upload output data 31 - - not in use. table 42: dma trigger sources
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 91 of 252 table 43: dma configuration data structure byte offset bit field name description 0 7:0 srcaddr[15:8] the dma channel source address, high 1 7:0 srcaddr[7:0] the dma channel source address, low 2 7:0 destaddr[15:8] the dma channel destination address, high. n ote that flash memory is not directly writeable. 3 7:0 destaddr[7:0] the dma channel destination address, high. n ote that flash memory is not directly writeable. 4 7:5 vlen[2:0] variable length transfer mode. in word mode, bits 12:0 of the first wo rd is considered as the transfer length. 000/111 use len for transfer count 001 transfer the number of bytes/words s pecified by first byte/word + 1 (up to a maximum specified by len). thus transfer count excludes length byte/word 010 transfer the number of bytes/words specified by first byte/word (up to a maximum specified by len). th us transfer count includes length byte/word. 011 transfer the number of bytes/words s pecified by first byte/word + 2 (up to a maximum specified by len). 100 transfer the number of bytes/words s pecified by first byte/word + 3 (up to a maximum specified by len). 101 reserved 110 reserved 4 4:0 len[12:8] the dma channel transfer count. used as maximum allowable length when vlen != 000/111. the dma channel counts in words when in wordsize mode, and otherwise in bytes. 5 7:0 len[7:0] the dma channel transfer count. used as maximum allowable length when vlen != 000/111. the dma channel counts in words when in wordsize mode, and otherwise in bytes. 6 7 wordsize selects whether each dma transfer shall be 8-bit (0) or 16-bit (1). 6 6:5 tmode[1:0] the dma channel transfer mode: 00 : single 01 : block 10 : repeated single 11 : repeated block 6 4:0 trig[4:0] select dma trigger to use 00000 : no trigger (writing to dmareq is only trigger) 00001 : the previous dma channel finished 00010 ? 11111 : selects one of the triggers shown in table 42. the trigger is selected in the order shown in the table. 7 7:6 srcinc[1:0] source address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words 7 5:4 destinc[1:0] destination address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 92 of 252 byte offset bit field name description 7 3 irqmask interrupt mask for this channel. 0 : disable i nterrupt generation 1 : enable interrupt generation upon dma channel done 7 2 m8 mode of 8 th bit for vlen transfer length; only applicable when wordsize=0. 0 : use all 8 bits for transfer count 1 : use 7 lsb for transfer count 7 1:0 priority[1:0] the dma channel priority: 00 : low, cpu has priority. 01 : guaranteed, dma at least every second try. 10 : high, dma has priority 11 : reserved.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 93 of 252 13.2.8 dma registers this section describes the sfr register s associated with the dma controller dmaarm (0xd6) ? dma channel arm bit name reset r/w description 7 abort 0 r0/w dma abort. this bit is used to stop ongoing dma transfers. writing a 1 to this bit will abort all channels which are selected by setting the corresponding dmaarm bit to 1 0 : normal operation 1 : abort channels all selected channels 6:5 - 00 r/w not used 4 dmaarm4 0 r/w dma arm channel 4 this bit must be set in order for any dma transfers to occur on the channel. for non-repetitive transfer modes, the bit is automatically cleared upon completion. 3 dmaarm3 0 r/w dma arm channel 3 this bit must be set in order for any dma transfers to occur on the channel. for non-repetitive transfer modes, the bit is automatically cleared upon completion. 2 dmaarm2 0 r/w dma arm channel 2 this bit must be set in order for any dma transfers to occur on the channel. for non-repetitive transfer modes, the bit is automatically cleared upon completion. 1 dmaarm1 0 r/w dma arm channel 1 this bit must be set in order for any dma transfers to occur on the channel. for non-repetitive transfer modes, the bit is automatically cleared upon completion. 0 dmaarm0 0 r/w dma arm channel 0 this bit must be set in order for any dma transfers to occur on the channel. for non-repetitive transfer modes, the bit is automatically cleared upon completion.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 94 of 252 dmareq (0xd7) ? dma channel start request and status bit name reset r/w description 7:5 - 000 r0 not used 4 dmareq4 0 r/w1 h0 dma transfer request, channel 4 manual trigger, set to 1 to start a transfer on the dma channel (has the same effect as a single trigger event.). this bit is cleared w hen the dma channel is granted access. 3 dmareq3 0 r/w1 h0 dma transfer request, channel 3 manual trigger, set to 1 to start a transfer on the dma channel (has the same effect as a single trigger event.). this bit is cleared w hen the dma channel is granted access. 2 dmareq2 0 r/w1 h0 dma transfer request, channel 2 manual trigger, set to 1 to start a transfer on the dma channel (has the same effect as a single trigger event.). this bit is cleared w hen the dma channel is granted access. 1 dmareq1 0 r/w1 h0 dma transfer request, channel 1 manual trigger, set to 1 to start a transfer on the dma channel (has the same effect as a single trigger event.). this bit is cleared w hen the dma channel is granted access. 0 dmareq0 0 r/w1 h0 dma transfer request, channel 0 manual trigger, set to 1 to start a transfer on the dma channel (has the same effect as a single trigger event.). this bit is cleared w hen the dma channel is granted access. dma0cfgh (0xd5) ? dma channel 0 configuration address high byte bit name reset r/w description 7:0 dma0cfg[15:8] 0x00 r/w the dma channel 0 configur ation address, high order dma0cfgl (0xd4) ? dma channel 0 configuration address low byte bit name reset r/w description 7:0 dma0cfg[7:0] 0x00 r/w the dma channel 0 configuration address, low order
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 95 of 252 dma1cfgh (0xd3) ? dma channel 1-4 configuration address high byte bit name reset r/w description 7:0 dma1cfg[15:8] 0x00 r/w the dma channel 1-4 configuration address, high order dma1cfgl (0xd2) ? dma channel 1-4 configuration address low byte bit name reset r/w description 7:0 dma1cfg[7:0] 0x00 r/w the dma channel 1-4 configuration address, low order dmairq (0xd1) ? dma interrupt flag bit name reset r/w description 7:5 - 000 r/w0 not used 4 dmaif4 0 r/w0 dma channel 4 interrupt flag. 0 : dma channel transfer not complete 1 : dma channel transfer complete/interrupt pending 3 dmaif3 0 r/w0 dma channel 3 interrupt flag. 0 : dma channel transfer not complete 1 : dma channel transfer complete/interrupt pending 2 dmaif2 0 r/w0 dma channel 2 interrupt flag. 0 : dma channel transfer not complete 1 : dma channel transfer complete/interrupt pending 1 dmaif1 0 r/w0 dma channel 1 interrupt flag. 0 : dma channel transfer not complete 1 : dma channel transfer complete/interrupt pending 0 dmaif0 0 r/w0 dma channel 0 interrupt flag. 0 : dma channel transfer not complete 1 : dma channel transfer complete/interrupt pending
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 96 of 252 endian (0x95) ? usb endianess control ( cc2511fx ) bit name reset r/w description 7:2 - 0 r0 not used. always 000000. usb write endianess setting for dma channel word transfers to usb. 0 big endian 1 usbwle 0 r/w 1 little endian usb read endianess setting for dm a channel word transfers from usb. 0 big endian 0 usbrle 0 r/w 1 little endian
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 97 of 252 13.3 16-bit timer, timer 1 timer 1 is an independent 16-bit timer which supports typical timer/ counter functions such as input capture, output compare and pwm functions. the timer has three independent capture/compare channels. the timer uses one i/o pin per channel. the timer is used for a wide range of control and measurement applications and the availability of up/down count mode with three channels will for example allow implementation of motor control applications. the features of timer 1 are as follows: ? three capture/compare channels ? rising, falling, or any edge input capture ? set, clear or toggle output compare ? free-running, modulo or up/down counter operation ? clock prescaler for divide by 1, 8, 32 or 128 ? interrupt request generated on each capture/compare and terminal count ? capture triggered by radio ? dma trigger function ? delta-sigma modulator (dsm) mode 13.3.1 16-bit timer counter the timer consists of a 16-bit counter that increments or decrements at each active clock edge. the period of the active clock edges is defined by the register bits clkcon.tickspd which sets the global division of the system clock giving a variable clock tick frequency from 0.203 mhz to 26 mhz for CC2510FX and 0.1875 mhz to 24 mhz for cc2511fx . this is further divided in timer 1 by the prescaler value set by t1ctl.div. this prescaler value can be from 1 to 128. thus the lowest clock frequency used by timer 1 is 1586.9 hz and the highest is 26 mhz when the 26 mhz crystal oscillator is used as system clock source ( CC2510FX ). the lowest clock frequency used by timer 1 is 1464.8 hz and the highest is 24 mhz for cc2511fx . when the 13 mhz rc oscillator is used as sy stem clock source, then the highest clock frequency used by timer 1 is 13 mhz. the counter operates as either a free-running counter, a modulo counter or as an up/down counter for use in centre-aligned pwm. it is possible to read the 16-bit counter value through the two 8-bit sfrs; t1cnth and t1cntl , containing the high-order byte and low-order byte respectively. when the t1cntl is read, the high-order byte of the counter at that instant is buffered in t1cnth so that the high-order byte can be read from t1cnth . thus t1cntl shall always be read first before reading t1cnth . all write accesses to the t1cntl register will reset the 16-bit counter. the counter produces an interrupt request when the terminal count value (overflow) is reached. it is possible to clear and halt the counter with t1ctl control register settings. the counter is started when a value other than 00 is written to t1ctl.mode . if 00 is written to t1ctl.mode the counter halts at its present value. 13.3.2 timer 1 operation in general, the control register t1ctl is used to control the timer operation. the various modes of operation are described below. 13.3.3 free-running mode in the free-running mode of operation the counter starts from 0x0000 and increments at each active clock edge. when the counter reaches 0xffff the counter is loaded with 0x0000 and continues incrementing its value as shown in figure 15. when the terminal count value 0xffff is reached, the flag t1ctl.ovfif is set. an interrupt request is generated if the corresponding interrupt mask bit timif.ovfim is set. the free-running mode can be used to generate independent time intervals and output signal frequencies.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 98 of 252 0000h ffffh overflow overflow figure 15: free-running mode 13.3.4 modulo mode when the timer operates in modulo mode the 16-bit counter starts at 0x0000 and increments at each active clock edge. when the counter reaches the terminal count value held in registers t1cc0h:t1cc0l , the counter is reset to 0x0000 and continues to increment. the flag t1ctl.ovfif is set when the terminal count value (overflow) is reached. an interrupt request is generated if the corresponding interrupt mask bit timif.ovfim is set. the modulo mode can be used for applications where a count value other then 0xffff is required. the counter operation is shown in figure 16. 0000h t1cc0 overflow overflow figure 16: modulo mode 13.3.5 up/down mode in the up/down timer mode, the counter repeatedly starts from 0x0000 and counts up until the value held in t1cc0h:t1cc0l is reached and then the counter counts down until 0x0000 is reached as shown in figure 17. this timer mode is used when symmetrical output pulses are required with a period other than 0xffff, and therefore allows implementation of centre-aligned pwm output applications. the flag t1ctl.ovfif is set when the timer turns around at 0x0000. the counter is reset to 0x000 by writing any value to t1cntl.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 99 of 252 figure 17 : up/down mode 13.3.6 channel mode control the channel mode is set with each channel?s control and status register t1cctln . the settings include input capture and output compare modes. 13.3.7 input capture mode when a channel is configured as an input capture channel, the i/o pin associated with that channel, is configured as an input. after the timer has been started, a rising edge, falling edge or any edge on the input pin will trigger a capture of the 16-bit counter contents into the associated capture register. thus the timer is able to capture the time when an external event takes place. note: before an i/o pin can be used by the timer, the required i/o pin must be configured as a timer 1 peripheral pin as described in section 13.1.4 on page 67 . the channel input pin is synchronized to the internal system clock. thus pulses on the input pin must have a minimum duration greater than the system clock period. the content of the 16-bi t capture register is read out from registers t1ccnh:t1ccnl . when the capture takes place the interrupt flag for the channel is set. this bit is t1ctl.ch0if for channel 0, t1ctl.ch1if for channel 1, and t1ctl.ch2if for channel 2. an interrupt request is generated if the corresponding interrupt mask bit on t1cctl0.im , t1cctl1.im , or t1cctl2.im , respectively, is set. 13.3.7.1 rf event capture each timer channel may be configured so that an rf interrupt rfif event will trigger a capture instead of the normal input pin capture. this function is selected with the register bit t1cctlx.cpsel which selects to use either the input pin or the rfif interrupt as capture event. when rfif is selected as capture input, the interrupt source(s) enabled by rfim (see section 15.3.1 on page 193) will trigger a capture. in this way the timer can be used to capture a value when e.g. a start of frame delimiter (sfd) is detected. 13.3.8 output compare mode in output compare mode the i/o pin associated with a channel is set as an output. after the timer has been started, the contents of the counter is compared with the contents of the channel compare register t1ccnh:t1ccnl . if the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of t1cctln.cmp . note that all edges on output pins are glitch-free when operating in a given output compare mode. writing to the compare register t1ccnl is buffered so that a value written to t1ccnl does not take effect until the corresponding high order register, t1ccnh is written. for output compare modes 1-3, a new value written to the compare register t1ccnh:t1ccnl takes effect after the registers have been written. for other output compare modes the new value written to the compare register take effect when the timer reaches 0x0000. note that channel 0 has fewer output compare modes than channel 1 and 2 because t1cc0h:t1cc0l has a special function in modes 6 and 7, meaning these modes would not be useful for channel 0. when a compare occurs, the interrupt flag for the channel is set. this bit is t1ctl.ch0if for channel 0, t1ctl.ch1if for channel 1, and t1ctl.ch2if for channel 2. an interrupt request is generated if the corresponding
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 100 of 252 interrupt mask bit on t1cctl0.im , t1cctl1.im , or t1cctl2.im , respectively, is set. examples of output compare modes in various timer modes are given in the following figures. edge-aligned pwm output signals can be generated using the timer modulo mode and channels 1 and 2 in output compare mode 5 or 6 as shown in figure 19. the period of the pwm signal is determined by the setting t1cc0 and the duty cycle for the channel output is determined by t1ccn . the timer free- running mode may also be used. in this case clkcon.tickspd and the prescaler divider value t1ctl.div set the period of the pwm signal. the polarity of the pwm signal is determined by whether output compare mode 5 or 6 is used. pwm output signals can also be generated using output compare modes 3 and 4 as shown in the same figure, or by using modulo mode as shown in figure 19. using output compare mode 3 and 4 is preferred for simple pwm. centre-aligned pwm outputs can be generated when the timer up/down mode is selected. the channel output compare mode 3 or 4 is selected depending on required polarity of the pwm signal. the period of the pwm signal is determined by t1cc0 and the duty cycle for the channel output is determined by t1ccn . in some types of applications, a defined delay or dead time is required between outputs. typically this is required for outputs driving an h-bridge configuration to avoid uncontrolled cross-conduction in one side of the h-bridge. the delay or dead-time can be obtained in the pwm outputs by using t1ccn as shown in the following: assuming that channel 1 and channel 2 are used to drive the outputs using timer up/down mode and the channels use output compare modes 3 and 4 respectively. if t1cc1 is greater than t1cc2, then the timer period (in timer 1 clock periods) is: t p = t1cc0 x 2 and the dead time, i.e. the time from when the channel 1 output goes low until the channel 2 output goes high, (in timer 1 clock periods) is given by: t d = t1cc1 ? t1cc2
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 101 of 252 figure 18: output compare modes, timer free-running mode
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 102 of 252 figure 19: output compare modes, timer modulo mode
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 103 of 252 figure 20: output modes, timer up/down mode 13.3.9 timer 1 interrupts there is one interrupt vector assigned to the timer. an interrupt request is generated when one of the following timer events occur: ? counter reaches terminal count value or turns around on zero ? input capture event. ? output compare event the register bits t1ctl.ovfif , t1ctl.ch0if , t1ctl.ch1if , and t1ctl.ch2if contains the interrupt flags for the terminal count value event, and the three channel compare/capture events, respectively. an interrupt request is only generated when the corresponding interrupt mask bit is set. the interrupt mask bits are t1cctl0.im , t1cctl1.im , t1cctl2.im and
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 104 of 252 timif.ovfim . if there are other pending interrupts, the corresponding interrupt flag must be cleared by software before a new interrupt request is generated. also, enabling an interrupt mask bit will generate a new interrupt request if t he corresponding interrupt flag is set. when the timer is used in free-running mode or modulo mode the interrupt flags are set as follows: ? t1ctl.ch0if, t1ctl.ch1if and t1ctl.ch2if are set on compare/capture event ? t1ctl.ovfif is set when counter reaches terminal count value when the timer is used in up/down mode the interrupt flags are set as follows: in compare mode: ? t1ctl.ch0if and t1ctl.ovfif are set when counter turns around on zero ? t1ctl.ch1if and t1ctl.ch2if are set on compare event in capture mode: ? t1ctl.ch0if, t1ctl.ch1if and t1ctl.ch2if are set on capture event ? t1ctl.ovfif is set when counter turns around on zero 13.3.10 timer 1 dma triggers there are three dma triggers associated with timer 1, one for each channel. these are dma triggers t1_ch0, t1_ch1 and t1_ch2 which are generated when the corresponding interrupt flags are set: ? t1_ch0 is generated when t1ctl.ch0if is set ? t1_ch1 is generated when t1ctl.ch0if is set ? t1_ch2 is generated when t1ctl.ch0if is set see table 42 for a list of all dma triggers. 13.3.11 dsm mode timer 1 also contains a 1-bit delta sigma modulator (dsm) of seco nd order that can be used to produce a high quality mono audio output pwm signal. the dsm removes the need for high order external filtering required when using regular pwm mode. the dsm operates at a fixed speed of either 1/4 or 1/8 of the timer 1 update speed ( clkcon.tickspd ) while input samples are updated at a configurable sampling rate set by timer 1 channel 0. an interpolator is used to match the sampling rate with the dsm update rate. this interpolator is of first order with a scaling compensation. the scaling compensation is due to variable gain defined by the difference in sampling speed and dsm speed. this interpolation mechanism can be disabled, thus using a zeroth interpolator. in addition to the interpolator, a shaper can be used to account for differences in rise/fall times in the output signal. this shaper ensures a rising and a falling edge per bit and will thus limits the output swing to the range 1/8 to 7/8 of i/o vdd when the dsm operates at 1/8 of the timer 1 update speed or 1/4 to 3/4 of i/o vdd when the dsm operates at 1/4 of the timer 1 update speed. the dsm is used as in pwm mode where channel 0 defines the period/sampling rate. the dsm can not use the timer 1 prescaler to further slow down the period. clkcon.tickspd , however, can be used. timer 1 channel 0 must be configured to compare modulo mode and have a terminal count value that matches the incoming sample rate. table 44 shows some timer 1 channel 0 periode settings ( t1cc0 register) for different timer 1 clock speeds and data rates (note that tick speed is not used, i.e. clkcon.tickspd = 000).
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 105 of 252 data rate t1cc0h t1cc0l 8 khz @ 24 mhz 0x0b 0xb7 8 khz @ 26 mhz 0x0c 0xb1 16 khz @ 24 mhz 0x05 0xdb 16 khz @ 26 mhz 0x06 0x59 48 khz @ 24 mhz 0x01 0xf3 48 khz @ 26 mhz 0x02 0x1d 64 khz @ 24 mhz 0x01 0x76 64 khz @ 26 mhz 0x01 0x96 table 44 channel 0 period setting for some sampling rates ( clkcon.tickspd = 000) the dsm starts immediately after dsm mode has been enabled by setting the t1cctl1.cmp field. thus, all configuration should have been performed prior to enabling dsm mode. also, the timer 1 counter should be cleared and started ju st before starting the dsm operation. a simple procedure for setting up dsm mode should then be as follows: 1. suspend timer 1 ( t1ctl.mode = 0) 2. clear timer counter by writing any value to t1cntl , ( t1cnt = 0x0000) 3. set the sample rate by writing the timer 1 channel 0 count period, t1cc0. 4. set timer 1 channel 0 compare mode ( t1cctl0.mode = 1) 5. load first sample if available (or zero if no sample available) into t1cc1h:t1cc1l . 6. set timer operation to modulo mode ( t1ctl.mode = 2) 7. configure the dsm by setting the mode and cap fields of the t1cct1 register. 8. enable dsm mode ( t1cctl1.cmp = 7) on each timer 1 irq or timer 1 dma trigger, write a new sample to the t1cc1h:t1cc1l registers. the least significant bits must be written to t1cc1l before the most significant bits are written to t1cc1h . the samples written must be signed 2?s complement values. the 2 least significant bits will always be treated as 0, thus the effective sample size is 14 bits. 13.3.12 timer 1 registers this section describes the timer 1 registers that consist of the following registers: ? t1cnth ? timer 1 count high ? t1cntl ? timer 1 count low ? t1ctl ? timer 1 control and status ? t1cctlx ? timer 1 channel x capture/compare control ? t1ccxh ? timer 1 channel x capture/compare value high ? t1ccxl ? timer 1 channel x capture/compare value low
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 106 of 252 t1cnth (0xe3) ? timer 1 counter high bit name reset r/w description 7:0 cnt[15:8] 0x00 r timer count high order byte. contains the high byte of the 16-bit timer counter buffered at the time t1cntl is read. t1cntl (0xe2) ? timer 1 counter low bit name reset r/w description 7:0 cnt[7:0] 0x00 r/w timer count low order byte. contains the low byte of the 16-bit timer counter. writing anything to this register results in the counter being cleared to 0x0000. t1ctl (0xe4) ? timer 1 control and status bit name reset r/w description 7 ch2if 0 r/w0 timer 1 channel 2 interrupt flag. set when the channel 2 interrupt condition occurs. writing a 1 has no effect. 6 ch1if 0 r/w0 timer 1 channel 1 interrupt flag. set when the channel 1 interrupt condition occurs. writing a 1 has no effect. 5 ch0if 0 r/w0 timer 1 channel 0 interrupt flag. set when the channel 0 interrupt condition occurs. writing a 1 has no effect. 4 ovfif 0 r/w0 timer 1 counter overflow interrupt flag. set when the counter reaches the terminal count value in free-running or modulo mode. writing a 1 has no effect. prescaler divider value. gener ates the active clock edge used to update the counter as follows: 00 tick frequency/1 01 tick frequency/8 10 tick frequency/32 3:2 div[1:0] 00 r/w 11 tick frequency/128 timer 1 mode select. the timer operating mode is selected as follows: 00 operation is suspended 01 free-running, repeatedly count from 0x0000 to 0xffff 10 modulo, repeatedly count from 0x0000 to t1cc0 1:0 mode[1:0] 00 r/w 11 up/down, repeatedly count from 0x0000 to t1cc0 and from t1cc0 down to 0x0000
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 107 of 252 t1cctl0 (0xe5) ? timer 1 channel 0 capture/compare control bit name reset r/w description capture select. timer 1 channel 0 captures on rfif interrupt from rf transceiver or capture input pin. 0 use normal capture input 7 cpsel 0 r/w 1 use rfif interrupt from rf transceiver for capture 6 im 1 r/w channel 0 interrupt mask. e nables interrupt request when set. channel 0 compare mode select. selects action on output when timer value equals compare value in t1cc0 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 not used 110 not used 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 1 channel 0 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 0 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on both edges t1cc0h (0xdb) ? timer 1 channel 0 capture/compare value high bit name reset r/w description 7:0 t1cc0[15:8] 0x00 r/w timer 1 channel 0 capture/c ompare value, high order byte t1cc0l (0xda) ? timer 1 channel 0 capture/compare value low bit name reset r/w description 7:0 t1cc0[7:0] 0x00 r/w timer 1 channel 0 capture/compare value, low order byte
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 108 of 252 t1cctl1 (0xe6) ? timer 1 channel 1 capture/compare control bit name reset r/w description capture select. timer 1 channel 1 captures on rfif interrupt from rf transceiver or capture input pin 0 use normal capture input 7 cpsel 0 r/w 1 use rfif interrupt from rf transceiver for capture 6 im 1 r/w channel 1 interrupt mask. e nables interrupt request when set. channel 1 compare mode select. selects action on output when timer value equals compare value in t1cc1 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 clear when equal t1cc0 , set when equal t1cc1 110 set when equal t1cc0 , clear when equal t1cc1 5:3 cmp[2:0] 000 r/w 111 dsm mode enable mode. select timer 1 channel 1 capture or compare mode. (timer mode) / select dsm update speed (dsm mode) 0 capture mode / dsm at timer/8 update speed 2 mode 0 r/w 1 compare mode / dsm at timer/4 update speed channel 1 capture mode select (timer mode) / dsm interpolator and output shaping configuration (dsm mode) 00 no capture / dsm interpolator and output shaping enabled 01 capture on rising edge / dsm interpolator enabled and output shaping disabled 10 capture on falling edge / dsm interpolator disabl ed and output shaping enabled 1:0 cap[1:0] 00 r/w 11 capture on all edges / dsm interpolator and output shaping disabled t1cc1h (0xdd) ? timer 1 channel 1 capture/compare value high bit name reset r/w description 7:0 t1cc1[15:8] 0x00 r/w timer 1 channel 1 capture/compa re value, high order byte (timer mode) dsm data high order byte (dsm mode)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 109 of 252 t1cc1l (0xdc) ? timer 1 channel 1 capture/compare value low bit name reset r/w description 7:0 t1cc1[7:0] 0x00 r/w timer 1 channel 1 capture/compa re value, low order byte (timer mode) dsm data low order byte. the two least significant bits are not used. (dsm mode) t1cctl2 (0xe7) ? timer 1 channel 2 capture/compare control bit name reset r/w description capture select. timer 1 channel 2 captures on rfif from rf transceiver or capture input pin 0 use normal capture input 7 cpsel 0 r/w 1 use rfif from rf transceiver for capture 6 im 1 r/w channel 2 interrupt mask. e nables interrupt request when set. channel 2 compare mode select. selects action on output when timer value equals compare value in t1cc2 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 clear when equal t1cc0 , set when equal t1cc2 110 set when equal t1cc0 , clear when equal t1cc2 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 1 channel 2 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 2 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on all edges t1cc2h (0xdf) ? timer 1 channel 2 capture/compare value high bit name reset r/w description 7:0 t1cc2[15:8] 0x00 r/w timer 1 channel 2 capture/c ompare value, high order byte
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 110 of 252 t1cc2l (0xde) ? timer 1 channel 2 capture/compare value low bit name reset r/w description 7:0 t1cc2[7:0] 0x00 r/w timer 1 channel 2 capture/compare value, low order byte the timif.ovfim register bit resides in the timif register, which is described together with timer 3 and timer 4
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 111 of 252 13.4 mac timer (timer 2) the mac timer is designed for slot timing operations for mac layers of rf protocols. the timer includes a highly tunable prescaler allowing the user to select a timer tick interval that equals, or is an integer fraction of a transmission slot. ? 8-bit timer ? 18-bit tunable prescaler 13.4.1 timer operation this section describes the operation of the timer. the timer count can be read from the t2ct sfr register. the timer decrements by 1 at each timer tick. when the timer count reaches 0x00 the timer expires and does not wrap around. when the timer expires, the register bit t2ctl.tex is set to 1. an interrupt request is generated when the timer expire s, if the interrupt mask t2ctl.int is 1. when a new value is written to the timer count register, t2ct, then this value is stored in the counter immediately. if a tick and a write to t2ct occurs at the same time, the written value will be decremented before it is stored. the timer tick period t, is given as: t = t2pr * val( t2ctl . tip ) clock cycles. where the function val(x) is set by the tick period, t2ctl . tip and defined as val(00)=64 val(01)=128 val(10)=256 val(11)=1024 the tick generator can be set to run freely or to run only when the timer holds a non- zero value. whenever the tick generator is started it starts from its zero state. at this point there will be t2pr *val( t2ctl . tip )-1 clock cycles until the next tick. 13.4.2 timer 2 registers the sfr registers associated with timer 2 are listed in this section. these registers are the following: ? t2ctl ? timer 2 control ? t2pre ? timer 2 prescaler ? t2ct ? timer 2 count
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 112 of 252 t2ctl (0x9e) ? timer 2 control bit name reset r/w description 7 - 0 r/w0 not used. 6 tex 0 r/w0 timer expired. this bit is set wh en the timer expires. writing a 1 to this bit has no effect 5 - 0 r/w reserved. should always be written as 0 4 int 0 r/w interrupt enable. select interrupt generated on timer expiration 0 interrupt disabled 1 interrupt enabled 3 - 0 r/w reserved. should always be written as 0 2 tig 0 r/w tick generator mode. 0 tick generator is running when t2ct not equal to 00h. the tick generator will always start running form its null state. 1 tick generator is in free-running m ode. if it is not already running it will start from its null state when a ?1? is written to tig. 1:0 tip[1:0] 00 r/w tick period. selects tick period based on prescaler multiplier value. 00 tick period is t2pr * 64 clock cycles 01 tick period is t2pr * 128 clock cycles 10 tick period is t2pr * 256 clock cycles 11 tick period is t2pr * 1024 clock cycles t2ct (0x9c) ? timer 2 count bit name reset r/w description 7:0 cnt[7:0] 0x00 r/w timer count. contents of 8-bit counter t2pr (0x9d) ? timer 2 prescaler bit name reset r/w description 7:0 pr[7:0] 0x00 r/w timer prescaler multiplier. 0x00 is interpreted as 256
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 113 of 252 13.5 sleep timer the sleep timer is used to control when the CC2510FX/cc2511fx exits from the low- power modes pm1 or pm2. thus the sleep timer can be used to implement a wake up functionality which enables CC2510FX/cc2511fx to periodically wake up from low-power mode and listen for incoming rf packets. additionally the sleep timer can be used as a real time clock when the 32.768 khz crystal oscillator is used. 13.5.1 sleep timer operation this section describes the operation of the timer. the sleep timer consists of a 31-bit counter. the appropriate bits of this counter are selected according to a resolution setting determined by the worctl.wor_res register bits. the sleep timer is either clocked by the 32.768 khz crystal oscillator or the 34.6667 khz (26mhz / 750) low power rc oscillator. the timer runs in all power modes except pm3 where all oscillat ors are powered off. the timer can be reset by writing 1 to the worctl.wor_reset register bit. the sleep timer has a programmable timing event called event 0. while in power mode pm1 or pm2, reaching event 0 will turn on the digital voltage regulator and start the crystal oscillator. the time between two consecutive event 0?s is programmed with timeout value set by a mantissa value given by worevt1.event0 and worevt0.event0 , and an exponent value set by worctrl.wor_res . the equation is: res wor xosc event event f t _ 5 0 2 0 750 ? ? ? = 13.5.2 low power rc oscillator and timing this section applies to using the low power rc oscillator as clock source for the sleep timer. the frequency of the low-power rc oscillator, which can be used as clock source for the sleep timer, varies with temperature and supply voltage. in order to keep the frequency as accurate as possible, the rc oscillator will be calibrated whenever possible, which is when the 26/48 mhz cr ystal oscillator is running and the chip is in the pm0 power mode. when the chip goes to pm1 or pm2, the rc oscillator will use the last valid calibration result. the frequency of the low power rc oscillator is therefore locked to the 26/48 mhz crystal oscillator frequency divided by 750. to generate a 32.768 khz rc oscillator frequency, use a 24.576 mhz crystal for the 26 mhz crystal oscillator. 13.5.3 sleep timer interrupt the sleep timer generates the sleep timer interrupt, st, when the timing event event 0 occurs. this interrupt source can be masked using the worirq.event0_mask interrupt mask bit. the interrupt flag bit worirq.event0_flag will be set when event 0 occurs. 13.5.4 sleep timer registers the sfr registers associated with the sleep timer are described in the following
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 114 of 252 wortime0 (0xa5) ? sleep timer low byte bit name reset r/w description 7:0 wortime0[7:0] 0x00 r timer 16-bit value, low byte. t he 16 bits are selected from the 31- bit sleep timer according to the setting of worctl.wor_res[1:0] wortime1 (0xa6) ? sleep timer high byte bit name reset r/w description 7:0 wortime1[15:8] 0x00 r timer 16-bit value, high byte. the 16 bits are selected from the 31-bit sleep timer according to the setting of worctl.wor_res[1:0] worevt1 (0xa4) ? sleep timer event0 timeout high bit name reset r/w description 7:0 event0[15:8] 0x87 r/w high byte of event 0 timeout register res wor xosc event event f t _ 5 0 2 0 750 ? ? ? = worevt0 (0xa3) ? sleep timer event0 timeout low bit name reset r/w description 7:0 event0[7:0] 107 (0x6b) r/w low byte of event 0 timeout register. the default event 0 value gives 1.0s timeout, assuming a 26.0 mhz crystal.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 115 of 252 worctl (0xa2) ? sleep timer control bit name reset r/w description 7 - 0 r0 not used 6:4 - 111 r/w not used. always write 111. 3 - - r0 not used 2 wor_reset 0 r0/w1 reset timer. if a 1 is wr itten to this bit location, the timer is reset. writing 0 will have no effect. always read as 0 1:0 wor_res[1:0] 00 r/w timer resolution controls the resolution and maximum timeout of the wor timer. adjusting the resolution does not affect the clock cycle counter: 00 31.25 us resolution, 2 s max timeout (15:0) 01 1 ms resolution, 65 s max timeout (20:5) 10 32 ms resolution, 35 min max timeout (25:10) 11 1 s resolution, 18 h max timeout (30:15) worirq (0xa1) ? sleep timer interrupt control bit name reset r/w description 7:6 - 00 r0 not used 5 - 0 r/w not used. this bit must always be written as 0. 4 event0_mask 0 r/w event 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled 3:2 - 00 r0 not used 1 - 0 r/w0 not used. this bit must always be written as 0. 0 event0_flag 0 r/w0 event 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 116 of 252 13.6 8-bit timer 3 and timer 4 timer 3 and 4 are 8-bit timers which support typical input capture and output compare operations using two capture/compare channels each. the timer allows general- purpose timer and waveform generation functions. features of timer 3/4 are as follows: ? dual channel operation ? rising, falling or any edge input compare ? set, clear or toggle output compare ? free-running, modulo or up/down counter operation ? clock prescaler for divide by 1, 2, 4, 8, 16, 32, 64, 128 ? interrupt request generated on each capture/compare and terminal count event ? dma trigger function 13.6.1 8-bit timer counter all timer functions are based on the main 8-bit counter found in timer 3/4. the counter increments or decrements at each active clock edge. the period of the active clock edges is defined by the register bits clkcon.tickspd which is further divided by the prescaler value set by txctl.div ( where x refers to the timer number, 3 or 4). the counter operates as either a free-running counter, a down counter, a modulo counter or as an up/down counter. it is possible to read the 8-bit counter value through the sfr txcnt where x refers to the timer number, 3 or 4. the possibility to clear and halt the counter is given with txctl control register settings. the counter is started when a 1 is written to txctl.start . if a 0 is written to txctl.start the counter halts at its present value. 13.6.2 timer 3/4 mode control in general the control register txctl is used to control the timer operation. the timer modes are described in the following sections. 13.6.2.1 free-running mode in the free-running mode of operation the counter starts from 0x00 and increments at each active clock edge. when the counter reaches 0xff the counter is loaded with 0x00 and continues incrementing its value. when the terminal count value 0xff is reached (i.e. an overflow occurs), the interrupt flag timif.txovfif is set. if the corresponding interrupt mask bit txctl.ovfim is set, an interrupt request is generated. the free- running mode can be used to generate independent time intervals and output signal frequencies. figure 21 free-running mode 13.6.2.2 down mode in the down mode, after the timer has been started, the counter is loaded with the contents in txcc . the counter then counts down to 0x00 and remains at 0x00. the flag timif.txovfif is set when 0x00 is reached. if the corresponding interrupt mask bit txctl.ovfim is set, an interrupt request is generated. the timer down mode can generally be used in applications where an event timeout interval is required.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 117 of 252 figure 22 down mode 13.6.2.3 modulo mode when the timer operates in modulo mode the 8-bit counter starts at 0x00 and increments at each active clock edge. when the counter reaches the value held in register txcc the counter is reset to 0x00 and continues to increment. the flag timif.txovfif is set on this event. if the corresponding interrupt mask bit txctl.ovfim is set, an interrupt request is generated. the modulo mode can be used for applications where a period other than 0xff is required. figure 23 modulo mode 13.6.2.4 up/down mode in the up/down timer mode, the counter repeatedly starts from 0x00 and counts up until the value held in txcc is reached and then the counter counts down until 0x00 is reached. this timer mode is used when symmetrical output pulses are required with a period other than 0xff, and therefore allows implementation of centre-aligned pwm output applications. the counter is reset to 0x00 by writing to txctl.clr .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 118 of 252 figure 24 up/down mode 13.6.3 channel mode control the channel modes for each channel are set by the control and status registers txcctln, where n is the channel number, 0 or 1. the settings include input capture and output compare modes. 13.6.4 input capture mode when the channel is configured as an input capture channel, the i/o pin associated with that channel is configured as an input. after the timer has been started, either a rising edge, a falling edge or any edge on the input pin triggers a capture of the 8-bit counter contents into the asso ciated capture register. thus the timer is able to capture the time when an external event takes place. the channel input pins ar e synchronized to the internal system clock. thus pulses on the input pins must have a minimum duration greater than the system clock period. note: before an input/output pin can be used by the timer, the required i/o pin must be configured as a timer 3/4 peripheral pin as described in sections 13.1.4.4 and 13.1.4.5. the contents of the 8-bit capture registers, is read out from registers txccn . when a capture takes place the interrupt flag corresponding to the actual channel is set. this interrupt flag is timif.txchnif . an interrupt request is generated if the corresponding interrupt mask bit txcctln.im is set. 13.6.5 output compare mode in output compare mode the i/o pin associated with a channel should be configured as an output. after the timer has been started, the contents of the counter is compared with the contents of the channel compare register txccn . if the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of txcctl.cmp1:0 . note that all edges on output pins are glitch-free when operating in a given compare output mode. for simple pwm use, output compare modes 3 and 4 are preferred. writing to the compare register txcc0 does not take effect on the output compare value until the counter value is 0x00. writing to the compare register txcc1 takes effect immediately. when a compare occurs the interrupt flag corresponding to the actual channel is set. this interrupt flag is timif.txchnif . an interrupt request is generated if the corresponding interrupt mask bit txcctln.im is set. 13.6.6 timer 3 and 4 interrupts there is one interrupt vector assigned to each of the timers. these are t3if (interrupt 11) and t4if (interrupt 12). an interrupt request is generated when one of the following timer events occur: ? counter reaches terminal count value. ? input capture event. ? output compare event the sfr register timif contains all interrupt flags for timer 3 and timer 4. the register bits timif.txovfif and timif.txchnif contain the interrupt flags for the two terminal count value events and the four channel compare/capture events, respectively. an interrupt request is only generated when the corresponding interrupt mask bit is set. if there are other pending interrupts, the
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 119 of 252 corresponding interrupt flag must be cleared by the cpu before a new interrupt request can be generated. also, enabling an interrupt mask bit will generate a new in terrupt request if the corresponding interrupt flag is set. when the timer is used in free-running mode or modulo mode the interrupt flags are set as follows: ? timif.txch0if and timif.txch1if are set on compare/capture event ? timif.txovfif is set when counter reaches terminal count value when the timer is used in up/down mode the interrupt flags are set as follows: in compare mode: ? timif.txch0if and timif.txovfif are set when the counter turns around on zero ? timif.txch1if is set on compare event in capture mode: ? timif.txch0if and timif.txch1if are set on capture event ? timif.txovfif is set when the counter turns around on zero 13.6.7 timer 3 and timer 4 dma triggers there are two dma triggers associated with timer 3 and two dma triggers associated with timer 4. these are dma triggers t3_ch0, t3_ch1, t4_ch0 and t4_ch1 which are generated when the corresponding interrupt flags are set: ? t3_ch0 is generated when timif.t3ch0if is set ? t3_ch1 is generated when timif.t3ch1if is set ? t4_ch0 is generated when timif.t4ch0if is set ? t4_ch1 is generated when timif.t4ch1if is set refer to section 13.2 on page 84, for a description on use of dma channels. 13.6.8 timer 3 and 4 registers the timer 3 and 4 registers are described on the following pages.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 120 of 252 t3cnt (0xca) ? timer 3 counter bit name reset r/w description 7:0 cnt[7:0] 0x00 r timer count byte. contains the current value of the 8-bit counter. t3ctl (0xcb) ? timer 3 control bit name reset r/w description prescaler divider value. gener ates the active clock edge used to clock the timer from clkcon.tickspd as follows: 000 tick frequency /1 001 tick frequency /2 010 tick frequency /4 011 tick frequency /8 100 tick frequency /16 101 tick frequency /32 110 tick frequency /64 7:5 div[2:0] 000 r/w 111 tick frequency /128 4 start 0 r/w start timer. normal operation when set, suspended when cleared 3 ovfim 1 r/w0 overflow interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled 2 clr 0 r0/w1 clear counter. writi ng high resets counter to 0x00 timer 3 mode. select the mode as follows: 00 free running, repeatedly count from 0x00 to 0xff 01 down, count from t3cc0 to 0x00 10 modulo, repeatedly count from 0x00 to t3cc0 1:0 mode[1:0] 00 r/w 11 up/down, repeatedly count from 0x00 to t3cc0 and down to 0x00
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 121 of 252 t3cctl0 (0xcc) ? timer 3 channel 0 capture/compare control bit name reset r/w description 7 - 0 r0 unused 6 im 1 r/w channel 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled channel 0 compare output mode select. specified action on output when timer value equals compare value in t3cc0 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 set output on compare, clear on 0xff 110 clear output on compare, set on 0x00 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 3 channel 0 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 0 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on all edges t3cc0 (0xcd) ? timer 3 channel 0 capture/compare value bit name reset r/w description 7:0 val[7:0] 0x00 r/w timer capture/compare value channel 0
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 122 of 252 t3cctl1 (0xce) ? timer 3 channel 1 capture/compare control bit name reset r/w description 7 - 0 r0 unused 6 im 1 r/w channel 1 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled channel 1 compare output mode select. specified action on output when timer value equals compare value in t3cc1 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 set output on compare, clear on t3cc0 110 clear output on compare, set on t3cc0 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 3 channel 1 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 1 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on all edges t3cc1 (0xcf) ? timer 3 channel 1 capture/compare value bit name reset r/w description 7:0 val[7:0] 0x00 r/w timer capture/compare value channel 1 t4cnt (0xea) ? timer 4 counter bit name reset r/w description 7:0 cnt[7:0] 0x00 r timer count byte. contains the current value of the 8-bit counter.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 123 of 252 t4ctl (0xeb) ? timer 4 control bit name reset r/w description prescaler divider value. gener ates the active clock edge used to clock the timer from clkcon.tickspd as follows: 000 tick frequency /1 001 tick frequency /2 010 tick frequency /4 011 tick frequency /8 100 tick frequency /16 101 tick frequency /32 110 tick frequency /64 7:5 div[2:0] 00 r/w 111 tick frequency /128 4 start 0 r/w start timer. normal operation when set, suspended when cleared 3 ovfim 1 r/w0 overflow interrupt mask 2 clr 0 r0/w1 clear counter. writi ng high resets counter to 0x00 timer 4 mode. select the mode as follows: 00 free running, repeatedly count from 0x00 to 0x00 01 down, count from t4cc0 to 0x00 10 modulo, repeatedly count from 0x00 to t4cc0 1:0 mode[1:0] 00 r/w 11 up/down, repeatedly count from 0x00 to t4cc0 and down to 0x00
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 124 of 252 t4cctl0 (0xec) ? timer 4 channel 0 capture/compare control bit name reset r/w description 7 - 0 r0 unused 6 im 1 r/w channel 0 interrupt mask channel 0 compare output mode select. specified action on output when timer value equals compare value in t4cc0 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 set output on compare, clear on 0x00 110 clear output on compare, set on 0x00 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 4 channel 0 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 0 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on all edges t4cc0 (0xed) ? timer 4 channel 0 capture/compare value bit name reset r/w description 7:0 val[7:0] 0x00 r/w timer capture/compare value channel 0
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 125 of 252 t4cctl1 (0xee) ? timer 4 channel 1 capture/compare control bit name reset r/w description 7 - 0 r0 unused 6 im 1 r/w channel 1 interrupt mask channel 1 compare output mode select. specified action on output when timer value equals compare value in t4cc1 000 set output on compare 001 clear output on compare 010 toggle output on compare 011 set output on compare-up, clear on 0 (clear on compare- down in up/down mode) 100 clear output on compare-up, set on 0 (set on compare- down in up/down mode) 101 set output on compare, clear on t4cc0 110 clear output on compare, set on t4cc0 5:3 cmp[2:0] 000 r/w 111 not used mode. select timer 4 channel 1 capture or compare mode 0 capture mode 2 mode 0 r/w 1 compare mode channel 1 capture mode select 00 no capture 01 capture on rising edge 10 capture on falling edge 1:0 cap[1:0] 00 r/w 11 capture on all edges t4cc1 (0xef) ? timer 4 channel 1 capture/compare value bit name reset r/w description 7:0 val[7:0] 0x00 r/w timer capture/compare value channel 1
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 126 of 252 timif (0xd8) ? timers 1/3/4 interrupt mask/flag bit name reset r/w description 7 - 0 r0 unused 6 ovfim 1 r/w timer 1 overflow interrupt mask 5 t4ch1if 0 r/w0 timer 4 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect. 4 t4ch0if 0 r/w0 timer 4 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect. 3 t4ovfif 0 r/w0 timer 4 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect. 2 t3ch1if 0 r/w0 timer 3 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect. 1 t3ch0if 0 r/w0 timer 3 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect. 0 t3ovfif 0 r/w0 timer 3 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending writing a 1 has no effect.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 127 of 252 13.7 adc 13.7.1 adc introduction the adc supports up to 14-bit analog-to- digital conversion. the adc includes an analog multiplexer with up to eight individually configurable channels, reference voltage generator and conversion results written to memory through dma. several modes of operation are available. the main features of the adc are as follows: ? selectable decimation rates which also sets the resolution (8 to 14 bits). ? eight individual input channels, single- ended or differential ? reference voltage selectable as internal, external single ended, external differential or avdd. ? interrupt request generation ? dma triggers at end of conversions ? temperature sensor input ? battery measurement capability input mux sigma-delta modulator decimation filter clock generation and control ain0 ain7 . . . ref mux input mux vdd/3 tmp_sensor int 1.25v ain7 avdd ain6-ain7 figure 25: adc block diagram. 13.7.2 adc operation this section describes the general setup and operation of the adc and describes the usage of the adc control and status registers accessed by the cpu. 13.7.2.1 adc core the adc includes an adc capable of converting an analog input into a digital representation with up to 14 bits resolution. the adc uses a selectable positive reference voltage. 13.7.2.2 adc inputs the signals on the p0 port pins can be used as adc inputs. in the following these port pint will be referred to as the ain0- ain7 pins. the input pins ain0-ain7 are connected to the adc. the adc can be set up to automatically perform a sequence of conversions and optionally perform an extra conversion from any channel when the sequence is completed. it is possible to configure the inputs as single-ended or differential inputs. in the case where differential inputs are selected,
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 128 of 252 the differential inputs consist of the input pairs ain0-1, ain2-3, ain4-5 and ain6-7. in addition to the input pins ain0-ain7, the output of an on-chip temperature sensor can be selected as an input to the adc for temperature measurements. it is also possible to select a voltage corresponding to avdd/3 as an adc input. this input allows the implementation of e.g. a battery monitor in applications where this feature is required. 13.7.2.3 adc conversion sequences the adc will perform a sequence of conversions, and move the results to memory (through dma) without any interaction from the cpu. the adccon2.sch register bits are used to define an adc conversion sequence, from the adc inputs. a conversion sequence will contain a conversion from each channel from 0 up to and including the channel number programmed in adccon2.sch when adccon2.sch is set to a value less than 8. the single-ended inputs ain0 to ain7 are represented by channel numbers 0 to 7 in adccon2.sch . channel numbers 8 to 11 represent the differential inputs consisting of ain0-ain1, ain2-ain3, ain4-ain5 and ain6-ain7. channel numbers 12 to 15 represent gnd, internal voltage reference, temperature sensor and avdd/3, respectively. when adccon2.sch is set to a value between 8 and 12, the sequence will start at channel 8. for even higher settings, only single conversions are performed. in addition to this sequence of conversions, the adc can be programmed to perform a single conversion from any channel as soon as the sequence has completed. this is called an extra conversion and is controlled with the adccon3 register. the conversion sequence can also be influenced with the adccfg register (see section 13.1.5 on page 69). the eight analog inputs to the adc come from i/o pins, which are not necessarily programmed to be analog inputs. if a channel should normally be part of a sequence, but the corresponding analog input is disabled in the adccfg , then that channel will be skipped. for channels 8 to 12, both input pins must be enabled. 13.7.2.4 adc operating modes this section describes the operating modes and initialization of conversions. the adc has three control registers: adccon1, adccon2 and adccon3. these registers are used to configure the adc and to report status. the adccon1.eoc bit is a status bit that is set high when a conversion ends and cleared when adch is read. the adccon1.st bit is used to start a sequence of conversi ons. a sequence will start when this bit is set high, adccon1.stsel=?11? and no conversion is currently running. when the sequence is completed, this bit is automatically cleared. the adccon1.stsel bits select which event that will start a new sequence of conversions. the options which can be selected are rising edge on external pin p2_0, end of previous sequence, a timer 1 channel 0 compare event or adccon1.st=?1?. the adccon2 register controls how the sequence of conversions is performed. adccon2.sref is used to select the reference voltage. the reference voltage should only be changed when no conversion is running. the adccon2.sdiv bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). the decimation rate should only be changed when no conversion is running. the last channel of a sequence is selected with the adccon2.sch bits. the adccon3 register controls the channel number, reference voltage and decimation rate for the extra conversion. the extra conversion will take place immediately after the adccon3 register is updated. the coding of the register bits is exactly as for adccon2 .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 129 of 252 13.7.2.5 adc conversion results the digital conversion result is represented in two's complement form. for 14-bit resolution, the digital conversion result is 8191 when the analogue input is equal to the vref, and the conversion result is -8192 when the analogue input is equal to ?vref, where vref is the selected positive voltage reference. when single-ended input is used, only positive conversion results are generated effectively reducing the resolution to maximum 13 bits. the digital conversion result is available when adccon1.eoc is set to 1, in adch and adcl . when reading the adccon2.sch field, the number returned will indicate the last channel converted. notice that when the value written to adccon2.sch is less than 12, the number returned will be the number of the last channel converted + 1. 13.7.2.6 adc reference voltage the positive reference voltage for analogue-to-digital conversions is selectable as either an internally generated 1.25v voltage, the avdd pin, the external voltage applied to the ain7 input pin or the differential voltage applied to the ain6-ain7 inputs. it is possible to select the reference voltage as the input to the adc in order to perform a conversion of the reference voltage e.g. for calibration purposes. similarly, it is possible to select the ground terminal gnd as an input. 13.7.2.7 adc conversion timing the 26/48 mhz crystal oscillator should be selected when the adc is used. the adc runs on a clock which is the 26/48 mhz system clock source divided by 6 to give a 4.33/4 mhz adc clock. the delta sigma modulator and decimation filter both use the adc clock for their calculations. the time required to perform a conversion depends on the selected decimation rate. when the decimation rate is set to for instance 128, the decimation filter uses exactly 128 of the adc clock periods to calculate the result. when a conversion is started, the input multiplexer is allowed 16 adc clock cycles to settle in case the channel has been changed since the previous conversion. the 16 clock cycles settling time applies to all decimation rates. thus in general, the conversion time is given by: tconv = (decimation rate + 16) x t where t = 0.23 s for CC2510FX t = 0.25 s for cc2511fx 13.7.2.8 adc interrupts the adc will generate an interrupt when an extra conversion has completed. an interrupt is not generated when a conversion from the sequence is completed. 13.7.2.9 adc dma triggers the adc will generate a dma trigger every time a conversion from the sequence has completed. when an extra conversion completes, no dma trigger is generated. there is one dma trigger for each of the eight channels defined by the first eight possible settings for adccon2.sch . the dma trigger is active when a new sample is ready from the conversion for the channel. the dma triggers are named adc_chx in table 42 on page 90. in addition there is one dma trigger, adc_chall, which is active when new data is ready from any of the channels in the adc conversion sequence. 13.7.2.10 adc registers this section describes the adc registers.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 130 of 252 adcl (0xba) ? adc data low bit name reset r/w description 7:2 adc[5:0] 0x00 r least significant part of adc conversion result. 1:0 - 00 r0 not used. always read as 0 adch (0xbb) ? adc data high bit name reset r/w description 7:0 adc[13:6] 0x00 r most significant part of adc conversion result. adccon1 (0xb4) ? adc control 1 bit name reset r/w description 7 eoc 0 r h0 end of conversion cleared w hen both adch and adcl has been read. if a new conversion is completed before the previous data has been read, the eoc bit will remain high. 0 conversion not complete 1 conversion completed 6 st 0 r/w1 start conversion. read as 1 until conversion has completed 0 no conversion in progress 1 start a conversion sequence if adccon1.stsel = ?11? and no sequence is running. 5:4 stsel[1:0] 11 r/w start select. selects which event that will start a new conversion sequence. 00 external trigger on p2_0 pin. 01 full speed. do not wait for triggers. 10 timer1 channel1 output = 1 11 adccon1.st = 1 3:2 rctrl[1:0] 00 r/w controls the 16 bit random generator. when written ?01?, the setting will automatically return to ?00? when operation has completed. 00 idle or operation completed. 01 clock the lfsr once (no unrolling). 10 reserved. 11 stopped. random generator is turned off. 1:0 - 11 r/w reserved. set to 11.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 131 of 252 adccon2 (0xb5) ? adc control 2 bit name reset r/w description selects reference voltage used fo r the sequence of conversions 00 internal 1.25v reference 01 external reference on ain7 pin 10 avdd pin 7:6 sref[1:0] 00 r/w 11 external reference on ain6-ain7 differential input sets the decimation rate for chann els included in the sequence of conversions. the decimation rate also determines the resolution and time required to complete a conversion. 00 64 dec rate (8 bits resolution) 01 128 dec rate (10 bits resolution) 10 256 dec rate (12 bits resolution) 5:4 sdiv[1:0] 01 r/w 11 512 dec rate (14 bits resolution) sequence channel select. selects the end of the sequence. a sequence can either be from ain0 to ain7 (sch<=7) or from the differential input ain0-ain1 to ain6-ain7 (8<=sch<=11). for other settings, only single c onversions are performed. when read, these bits will indica te the channel number of current conversion result when sch >= 12. when sch <= 11, these bits will indicate the channel number of current conversion result +1. 0000 ain0 0001 ain1 0010 ain2 0011 ain3 0100 ain4 0101 ain5 0110 ain6 0111 ain7 1000 ain0-ain1 1001 ain2-ain3 1010 ain4-ain5 1011 ain6-ain7 1100 gnd 1101 positive voltage reference 1110 temperature sensor 3:0 sch[3:0] 00 r/w 1111 avdd/3
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 132 of 252 adccon3 (0xb6) ? adc control 3 bit name reset r/w description selects reference voltage used for the extra conversion 00 internal 1.25v reference 01 external reference on ain7 pin 10 avdd pin 7:6 eref[1:0] 00 r/w 11 external reference on ain6-ain7 differential input sets the decimation rate used fo r the extra conversion. the decimation rate also determines the resolution and time required to complete the conversion. 00 64 dec rate (8 bits resolution) 01 128 dec rate (10 bits resolution) 10 256 dec rate (12 bits resolution) 5:4 ediv[1:0] 00 r/w 11 512 dec rate (14 bits resolution) extra channel select. selects the channel number of the extra conversion that is carried out afte r a conversion sequence has ended. if the adc is not running, writing to these bits will trigger an immediate single conversion from the selected extra channel. the bits are automatically cleared when the extra conversion has finished. 0000 ain0 0001 ain1 0010 ain2 0011 ain3 0100 ain4 0101 ain5 0110 ain6 0111 ain7 1000 ain0-ain1 1001 ain2-ain3 1010 ain4-ain5 1011 ain6-ain7 1100 gnd 1101 positive voltage reference 1110 temperature sensor 3:0 ech[3:0] 0000 r/w 1111 vdd/3
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 133 of 252 13.8 random number generator 13.8.1 introduction the random number generator has the following features. ? generate pseudo-random bytes which can be read by the cpu. ? calculate crc16 of bytes that are written to rndh . ? seeded by value written to rndl . the random number generator is a 16-bit linear feedback shift register (lfsr) with polynomial 1 2 15 16 + + + x x x (i.e. crc16). it uses different levels of unrolling depending on the operation it performs. the basic version (no unrolling) is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + + in_bit figure 26: basic structure of the random number generator the random number generator is turned off when adccon1.rctrl =?11?. 13.8.2 random number generator operation the operation of the random number generator is controlled through a combination of the adccon1.rctrl bits and input signals from other modules. the current value of the 16-bit shift register in the lfsr can be read from the rndh and rndl registers. 13.8.2.1 semi random sequence generation the lfsr is updated by setting adccon1.rctrl=?01? . this will clock the lfsr once (no unrolling) and the adccon1.rctrl bits will automatically be cleared when the operation has completed. 13.8.2.2 seeding the lfsr is seeded from software by writing to the rndl register twice. each time the rndl register is written, the 8 lsb of the lfsr is copied to the 8 msb and the 8 lsbs are replaced with the new data byte that was written to rndl . 13.8.2.3 crc16 the lfsr can also be used to calculate the crc value of a sequence of bytes. writing to the rndh register will trigger a crc calculation. the new byte is processed from the msb end and an 8x unrolling is used, so that a new byte can be written to rndh every clock cycle. note that the lfsr must be properly seeded by writing to rndl , before the crc calculations start. commonly used seed values are 0x0000 or 0xffff. 13.8.3 registers the random number generator registers are described in this section.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 134 of 252 rndl (0xbc) ? random number generator data low byte bit name reset r/w description [7:0] rndl[7:0] 0xff r/w random value/seed or crc result, low byte when used for random number gener ation writing this register twice will seed the random number generator. writing to this register copies the 8 lsbs of the lfsr to the 8 msbs and replaces the 8 lsbs with the data value written. the value returned when reading from this register is the 8 lsbs of the lsfr. when used for random number gener ation, reading this register returns the 8 lsbs of the random number. when used for crc calculations, reading this regis ter returns the 8 lsbs of the crc result. rndh (0xbd) ? random number generator data high byte bit name reset r/w description [7:0] rndh[7:0] 0xff r/w random value or crc result/input data, high byte when written, a crc16 calculation will be triggered, and the data value written is process ed starting with the msb bit. the value returned when reading from this register is the 8 msbs of the lsfr. when used for random number gener ation, reading this register returns the 8 msbs of the random number. when used for crc calculations, reading this regis ter returns the 8 msbs of the crc result.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 135 of 252 13.9 aes coprocessor with the CC2510FX/cc2511fx , data encryption can be performed using a dedicated coprocessor which supports advanced encryption standard, aes. the coprocessor allows encryption/decryption to be performed with minimal cpu usage. the coprocessor has the following features: ? ecb, cbc, cfb, ofb, ctr and cbc- mac modes. ? hardware support for ccm mode ? 128-bits key and iv/nonce ? dma transfer trigger capability 13.9.1 aes operation to encrypt a message, the following procedure must be followed: ? load key ? load initialization vector (iv) ? download and upload data for encryption/decryption. the aes coprocessor works on blocks of 128 bits. a block of data is loaded into the coprocessor, encryption is performed and the result must be read out before the next block can be processed. before each block load, a dedicated start command must be sent to the coprocessor. 13.9.2 key and iv before a key or iv/nonce load starts, an appropriate load key or iv must be issued to the coprocessor. when loading the iv it is important to also set the correct mode. a key load or iv load operation aborts any processing that could be running. the key, once loaded, stays valid until a key reload takes place. the iv must be downloaded before the beginning of each message (not block). both key and iv are cleared by a reset. 13.9.3 padding of input data aes works on blocks of 128 bits. if the last block contains less than 128 bits, it must be padded with zeros when written to the coprocessor. 13.9.4 interface to cpu the cpu communicates with the coprocessor using three sfr registers: ? enccs , encryption control and status register ? encdi , encryption input register ? encdo , encryption output register read/write to the status register is done by the cpu, while read/wr ite the input/output register is intended for use together with direct memory access (dma). two dma channels must be used, one for input data and one for output data. the dma channels must be initialized before a start command is written to the enccs . writing a start command generates a dma trigger and the transfer is started. after each block is processed, an interrupt is generated. the interrupt is used to issue a new start command to the enccs . 13.9.5 modes of operation ecb and cbc modes are performed as described in section 13.9.1 when using cfb, ofb and ctr mode, the 128 bits blocks are divided into four 32 bits blocks. 32 bits are loaded into the aes coprocessor and the resulting 32 bits are read out. this continues until all 128 bits are encrypted. the only time one has to consider this is if data is loaded/read directly using the cpu. when using dma, this is handled automatically by the dma triggers generated by the aes coprocessor. both encryption and decryption are performed similarly. the cbc-mac mode is a variant of the cbc mode. when performing cbc-mac, data is downloaded to the coprocessor as one block at a time, except for the last block. before the last block is loaded, the mode must be changed to cbc. the last block is then downloaded and the block uploaded will be the mac value.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 136 of 252 ccm is a combination of cbc-mac and ctr. parts of the ccm must therefore be done in software. the following section gives a short explanation of the necessary steps to be done. 13.9.5.1 cbc-mac when performing cbc-mac encryption, data is only downloaded to the coprocessor in cbc-mac mode except for the last block, one block at a time. before the last block is loaded, the mode is changed to cbc. the last block is downloaded and the block uploaded is the message mac. cbc-mac decryption is similar to encryption. the message mac uploaded must be compared with the mac to be verified. 13.9.5.2 ccm mode to encrypt a message under ccm mode, the following sequence can be conducted (key is already loaded): message authentication phase this phase takes place during steps 1-6 shown in the following. (1) the software loads the iv with zeros. (2) the software creates the block b0. the layout of block b0 is shown in figure 27. . name b0 designation first block for authentication in ccm mode byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 name flag nonce l_m figure 27: message authentication phase block 0 there is no restriction on the nonce value. l_m is the message length in bytes. the content of the authentication flag byte is described in figure 28. l is set to 6 in this example. so, l-1 is set to 5. m and a_data can be set to any value. name flag/b0 designation authentication flag field for ccm mode bit 7 6 5 4 3 2 1 0 name reserved a_data (m-2)/2 l-1 value 0 x x x x 1 0 1 figure 28: authentication flag byte (3) if some additional authentication data (called a later) is needed (that is a_data =1), the software creates the a_data length field, called l(a) by : ? (3a) if l(a)=0, (that is a_data =0), then l(a) is the empty string. we note l(a) the length of a in octets. ? (3b) if 0 < l(a) < 2 16 - 2 8 , then l(a) is the 2-octets encoding of l(a).
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 137 of 252 the additional authentication data is appended to the a_data length field l(a). the additional authentication blocks is padded with zeros until the last additional authentication block is full. there is no restriction on the length of a. auth-data = l(a) + authentication data + (zero padding) ( 4) the last block of the message is padded with 0s until full (that is if its length is not a multiple of 128). (5) the software concatenates the block b0, the additional authentication blocks if any, and the message; input message = b0 + auth-data + message + (zero padding of message) (6) once the input message authentication by cbc-mac is finished, the software leaves the uploaded buffer contents unchanged (m=16), or keeps only the buffer?s higher m bytes unchanged, while setting the lower bits to 0 (m != 16). the result is called t. message encryption (7) the software creates the key stream block a0. note that l= 6, with the current example of the ctr generation. the content is shown in figure 29: name a0 designation first ctr value for ccm mode byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 name flag nonce ctr figure 29: message encryption phase block 0 note that any value but zero works for the ctr value. the content of the encryption flag byte is described in figure 30 name flag/a0 designation encryption flag field for ccm mode bit 7 6 5 4 3 2 1 0 name reserved - l-1 value 0 0 0 0 0 1 0 1 figure 30: encryption flag byte ( 8) the software loads a0 by selecting a load iv/nonce command. to do so, it sets mode to cfb or ofb at the same time it selects the load iv/nonce command. (9) the software calls a cfb or an ofb encryption on the authenticated data t. the uploaded buffer contents stay unchanged (m=16), or only its first m bytes stay unchanged, the others being set to 0 (m-16). the result is u, which will be used later. ( 10) the software calls a ctr mode encryption right now on the still padded message blocks. it does not have to reload the iv/ctr. (11) the encrypted authentication data u is appended to the encrypted message. this gives the final result, c. result c = encrypted message(m) + u message decrypt ion
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 138 of 252 ccm mode decryption in the coprocessor, the automatic generation of ctr works on 32 bits, therefore the maximum length of a message is 128 x 2 32 bits, that is 2 36 bytes, which can be written in a six-bit word. so, the value l is set to 6. to decrypt a ccm mode processed message, the following sequence can be conducted (key is already loaded): message parsing phase (1) the software parses the message by separating the m rightmost octets, namely u, and the other octets, namely string c. (2) c is padded with zeros until it can fill an integer number of 128-bit blocks; (3) u is padded with ze ros until it can fill a 128-bit block. (4) the software creates the key stream block a0. it is done the same way as for ccm encryption. (5) the software loads a0 by selected a load iv/nonce command. to do so, it sets mode to cfb or ofb at the same time it selects the iv load. (6) the software calls a cfb or an ofb encryption on the encrypted authenticated data u. the uploaded buffer contents stay unchanged (m=16), or only its first m bytes stay unchanged, the others being set to 0 (m!=16). the result is t. ( 7) the software calls a ctr mode decryption right now on the encrypted message blocks c. it does not have to reload the iv/ctr. reference authentication tag generation this phase is identical to the authentication phase of ccm encryption. the only difference is that the result is named mactag (instead of t). message authentication checking phase the software compares t with mactag. 13.9.6 sharing the aes coprocessor between layers the aes coprocessor is a common resource shared by all layers. the aes coprocessor can only be used by one instance one at a time. it is therefore necessary to implement some kind of software semaphore to allocate and de- allocate the resource. 13.9.7 aes interrupts the aes interrupt, enc, is produced when encryption or decryption of a block is completed. the interrupt enable bit is ien0.encie and the interrupt flag is s0con.encif . 13.9.8 aes dma triggers there are two dma triggers associated with the aes coprocessor. these are enc_dw which is active when input data needs to be downloaded to the encdi register, and enc_up which is active when output data needs to be uploaded from the encdo register. the encdi and encdo registers should be set as destination and source locations for dma channels used to transfer data to or from the aes coprocessor. 13.9.9 aes registers the aes coprocessor registers have the layout shown in this section.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 139 of 252 enccs (0xb3) ? encryption control and status bit name reset r/w description 7 - 0 r0 not used, always read as 0 encryption/decryption mode 000 cbc 001 cfb 010 ofb 011 ctr 100 ecb 101 cbc mac 110 not used 6:4 mode[2:0] 000 r/w 111 not used encryption/decryption ready status 0 encryption/decryption in progress 3 rdy 1 r 1 encryption/decryption is completed command to be performed when a 1 is written to st . 00 encrypt block 01 decrypt block 10 load key 2:1 cmd[1:0] 0 r/w 11 load iv/nonce 0 st 0 r/w1 h0 start processing command set by cmd. must be issued for each command or 128 bits block of data. cleared by hardware encdi (0xb1) ? encryption input data bit name reset r/w description 7:0 din[7:0] 0x00 r/w encryption input data encdo (0xb2) ? encryption output data bit name reset r/w description 7:0 dout[7:0] 0x00 r/w encryption output data
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 140 of 252 13.10 power management this section describes the power management controller. the power management controller controls the use of power modes and clock control to achieve low-power operation. 13.10.1 power management introduction the CC2510FX/cc2511fx uses different operating modes, or power modes, to allow low-power operation. ultra-low- power operation is obtained by turning off power supply to modules to avoid static (leakage) power consumption and also by using clock gating to reduce dynamic power consumption. the various operating modes are enumerated and shall be designated as power modes (pmx). the power modes are: ? pm0 clock oscillators on, voltage regulator on ? pm1 32.768/34 khz oscillators on, voltage regulator on ? pm2 32.768/34 khz oscillators on, voltage regulator off ? pm3 all clock oscillators off, voltage regulator off 13.10.1.1 pm0 pm0 is the full functional mode of operation where the cpu and peripherals are active. the voltage regulator is turned on. pm0 is used for normal operation. 13.10.1.2 pm1 in pm1, the high-speed oscillators are powered down thereby halting the cpu and peripherals. the voltage regulator, the power-on reset, external interrupts, the 32.768/34 khz oscillators and sleep timer peripherals are active. i/o pins retain the i/o mode and output value set before entering pm1. when pm1 is entered, a power down sequence is run. when the device is taken out of pm1 to pm0, the high-speed oscillators are started. the device will run on t he high speed rc oscillator until the high speed crystal oscillator has se ttled and has been selected. pm1 is used when the expected time until a wakeup event is relatively short since pm1 uses a fast power down/up sequence. 13.10.1.3 pm2 pm2 has the second lowest power consumption. in pm2 the power-on reset, external interrupts, 32.768/34 khz oscillators and sleep timer peripherals are active. i/o pins retain the i/o mode and output value set before entering pm2. all other internal circuits are powered down. the voltage regulator is also turned off. when pm2 is entered, a power down sequence is run. pm2 is used when it is relatively long until the expected time of a wakeup event, since the power up/down sequence is relatively long. pm2 is typically entered when using the sleep timer as the wakeup event. 13.10.1.4 pm3 pm3 is used to achieve the operating mode with the lowest power consumption. in pm3 all internal circuits that are powered from the voltage regulator are turned off. the intern al voltage regulator and all oscillators are also turned off. power-on reset and external interrupts are the only functions that are operating in this mode. i/o pins retain the i/o mode and output value set before entering pm3. only a reset or external interrupt condition will wake the device up and place it into pm0. the contents of ram and registers are preserved in this mode. pm3 uses the same power down/up sequence as pm2. pm3 is used to achieve ultra low power consumption when waiting for an external event. 13.10.2 power management control the required power mode is selected by the mode bits in the sleep control
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 141 of 252 register. setting the sfr register pcon.idle bit after setting the mode bits, enters the selected power mode. an interrupt from port pins, or sleep timer (not pm3) or a power-on reset will wake the device and bring it into pm0 by resetting the mode bits. 13.10.3 system clock the system clock is derived from the selected main clock source, which is the high-speed (26/48 mhz) crystal oscillator or the high-speed (13 mhz) rc oscillator. the clkcon.osc bit selects the source of the main system clock. note that to use the rf transceiver the high speed crystal oscillator must be selected and stable. when the sleep.xosc_stb is 1, the 26/48 mhz crystal oscillator is stable and can be used as the source for the system clock. the oscillator not selected as the system clock source, will be set in power-down mode by setting sleep.osc_pd to 1. thus the high-speed rc oscillator may be turned off when the 26/48 mhz crystal oscillator has been selected as system clock source and vice versa. when sleep.osc_pd is 0, both oscillators are powered up and running. the selected main clock source can be divided down by setting the clkcon.clkspd register appropriately. eight different system clock frequencies from 0.203 to 26 mhz for CC2510FX or from 0.1875 to 24 mhz for cc2511fx can be used. 13.10.4 high-speed oscillators two high speed oscillators are present in the device. the high-speed crystal oscillator startup time may be too long for some applications, therefore the device will run on the high -speed rc oscillator until crystal oscillator is stable. the high- speed rc oscillator co nsumes less power than the crystal oscillator, but since it is not as accurate as the crystal oscillator it can not be used for rf transceiver operation. 13.10.5 32.768/34 khz oscillators two low power oscillato rs are present in the device. by default the low power rc oscillator is enabled (see table 12 on page 16). the low power rc oscillator consumes less power, but is less accurate than the 32.768 khz crystal oscillator. when the high speed crystal oscillator is running the low power rc oscillator is continuously calibrated. it is calibrated to a frequency equal to high speed crystal frequency divided by 750. e.g. 34.67 khz with 26 mhz crystal ( CC2510FX ) and 32 khz with 24 mhz crystal ( cc2511fx ). 13.10.6 timer tick generation the power management controller generates a tick or enable signal for the peripheral timers, thus acting as a prescaler for the timers. this is a global clock division for timer 1, timer 3 and timer 4. the tick speed is programmed from 0.203 to 26 mhz for CC2510FX or from 0.1875 to 24 mhz for cc2511fx by setting the clkcon.tickspd register appropriately. note: the clkcon.tickspd register cannot be set higher than clkcon.clkspd . 13.10.7 data retention in power modes pm2 and pm3 parts of sram will retain its contents. the content of internal registers is also retained in pm2/3. the xdata memory locations 0xf000- 0xffff (4096 bytes) retains data in pm2/3. please note one exception as given below. the xdata memory locations 0xfda2- 0xfeff (350 bytes) will lose all data when pm2/3 is entered. these locations will contain undefined data when pm0 is re- entered. the registers which retain their contents are the cpu registers, peripheral registers and rf registers, therefore switching to the low-power modes pm2/3 appears transparent to software. 13.10.8 i/o and radio i/o port pins p1_0 and p1_1 do not have internal pull-up/pull-down resistors. these
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 142 of 252 pins should therefore be set as outputs or pulled high/low externally to avoid leakage current. to save power, the radio should be turned off when it is not used. 13.10.9 power management registers this section describes the power management registers. pcon (0x87) ? power mode control bit name reset r/w description 7:2 - 0x00 r/w not used. 1 - 0 r0 not used, always read as 0. 0 idle 0 r0/w h0 power mode control. writing a 1 to this bit forces entry to the power mode set by sleep.mode . this bit is always read as 0 sleep (0xbe) ? sleep mode control bit name reset r/w description 7 usb_en 0 r/w usb enable ( cc2511fx ). this bit is unused for CC2510FX . 0 ? usb disabled 1 ? usb enabled 6 xosc_stb 0 r 26/48 mhz crystal o scillator stable status: 0 ? oscillator is not powered up or not yet stable 1 ? oscillator is powered up and stable 5 hfrc_stb 0 r high speed rc osci llator stable status: 0 ? oscillator is not powered up or not yet stable 1 ? oscillator is powered up and stable 4:3 rst[1:0] xx r reserved. 2 osc_pd 1 r/w h0 xosc and hs rcosc power down setting. the bit is cleared if the clkcon.osc bit is toggled. also, if there is a calibration in progress and the cpu attempts to set the bit, the bit will be updated at the end of calibration: 0 ? both oscillators powered up 1 ? oscillator not selected by clkcon.osc bit powered down 1:0 mode[1:0] 00 r/w sleep mode setting: 00 ? power mode 0 01 ? power mode 1 10 ? power mode 2 11 ? power mode 3
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 143 of 252 clkcon (0xc6) ? clock control bit name reset r/w description 7 osc32k 1 r/w 32 khz clock oscillator select: 0 ? 32.768 khz crystal oscillator 1 ? 34 khz low power rc oscillator 6 osc 1 r/w main clock oscillator select: 0 ? 26/48 mhz crystal oscillator 1 ? 13 mhz hf rc oscillator this setting will only take effect when the selected oscillator is powered up and stable. if the selected oscillator is not powered up, then writing this bit will power it up. timer ticks output setting. the value of tickspd cannot be higher than clkspd . CC2510FX cc2511fx 000 26 mhz 24 mhz 001 13 mhz 12 mhz 010 6.5 mhz 6 mhz 011 3.25 mhz 3 mhz 100 1.625 mhz 1.5 mhz 101 812.5 khz 750 khz 110 406.25 khz 325 khz 5:3 tickspd[2:0] 001 r/w 111 203.125 khz 162.5 khz clock speed setting. when a new clkspd value is written, the new setting is read when the clock has changed. CC2510FX cc2511fx 000 26 mhz 24 mhz 001 13 mhz 12 mhz 010 6.5 mhz 6 mhz 011 3.25 mhz 3 mhz 100 1.625 mhz 1.5 mhz 101 812.5 khz 750 khz 110 406.25 khz 325 khz 2:0 clkspd[2:0] 001 r/w 111 203.125 khz 162.5 khz
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 144 of 252 13.11 power on reset the CC2510FX/cc2511fx includes a power on reset (por) in order to protect the memory contents during supply voltage variations and provide correct initialization during power-on. when power is initially applied to the CC2510FX/cc2511fx the power on reset (por) will hold the device in reset state until the supply voltage reaches above the power on reset voltage as defined in table 5 on page 11. figure 31 shows the por operation with the 1.8v (typical) regulated supply voltage together with the active low reset signal shown in the bottom of the figure. the cause of the last reset can read from the register bits sleep.rst . 0 unregulated 1.8v regulated por reset assert falling vdd por reset deassert rising vdd volt por reset x x figure 31 : power on reset operation
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 145 of 252 13.12 watchdog timer the watchdog timer (wdt) is intended as a recovery method in situations where the software hangs. the wdt shall reset the system when software fails to clear the wdt within a selected time interval. the watchdog can be used in applications that are subject to electrical noise, power glitches, electrostatic discharge etc., or where high reliability is required. if the watchdog function is not needed in an application, it is possible to configure the watchdog timer to be used as an interval timer that can be used to generate interrupts at selected time intervals. the features of the watchdog timer are as follows: ? four selectable timer intervals ? watchdog mode ? timer mode ? interrupt request generation in timer mode ? clock independent from system clock the wdt is configured as either a watchdog timer or as a timer for general- purpose use. the operation of the wdt module is controlled by the wdctl register. the watchdog timer consists of an 15-bit counter clocked by the 32.768 oscillator or 32 - 34 khz rc clock. note that the contents of the 15-bit counter is not user-accessible. 13.12.1 watchdog mode the watchdog timer is disabled after a system reset. to set the wdt in watchdog mode the wdctl.mode bit is set to 0. the watchdog timer counter starts incrementing when the enable bit wdctl.en is set to 1. when the timer is enabled in watchdog mode it is not possible to disable the timer. therfore, writing a 0 to wdctl.en has no effect if a 1 was already written to this bit when wdctl.mode was 0. the wdt can operate with a watchdog timer clock frequency of 32.768 khz. this clock frequency gives time-out periods equal to 1.9 ms, 15.625 ms, 0.25 s and 1 s corresponding to the count value settings 64, 512, 8192 and 32768 respectively. if the counter reaches the selected timer interval value, the watchdog timer generates a reset signal for the system. if a watchdog clear sequence is performed before the counter reaches the selected timer interval value, the counter is reset to 0x0000 and continues incrementing its value. the watchdog clear sequence consists of writing 0xa to wdctl.clr[3:0] followed by writing 0x5 to the same register bits within one half of a watchdog clock period. if this complete sequence is not performed, the watchdog timer generates a reset signal for the system. note that as long as a correct watchdog clear sequence begins within the selected timer interval, the counter is reset when the complete sequence has been received. when the watchdog timer has been enabled in watchdog mode, it is not possible to change the mode by writing to the wdctl.mode bit. the timer interval value can be changed by writing to the wdctl.int[1:0] bits. note that it is recommended that user software clears the watchdog timer at the same time as the timer interval value is changed, in order to avoid an unwanted watchdog reset. in watchdog mode, the wdt does not produce an interrupt request. 13.12.2 timer mode to set the wdt in normal timer mode, the wdctl.mode bit is set to 1. when register bit wdctl.en is set to 1, the timer is started and the counter starts incrementing. when the counter reaches the selected interval value, the timer will produce an interrupt request. in timer mode, it is possible to clear the timer contents by writing a 1 to wdctl.clr[0] . when the timer is cleared the contents of the counter is set to 0x0000. writing a 0 to the enable bit wdctl.en stops the timer and writing 1 restarts the timer from 0x0000. the timer interval is set by the wdctl.int[1:0] bits. in timer mode, a
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 146 of 252 reset will not be produced when the timer interval has been reached. 13.12.3 watchdog timer example figure 32 shows an example of periodical clearing of an active watchdog timer. ; clear watchdog timer mov wdctl,#abh mov wdctl,#5bh figure 32: wdt example 13.12.4 watchdog timer register this section describes the register for the watchdog timer. wdctl (0xc9) ? watchdog timer control bit name reset r/w description 7:4 clr[3:0] 0000 r/w clear timer. when 0xa followed by 0x5 is written to these bits, the timer is loaded with 0x0. note the timer will only be cleared when 0x5 is written within 0.5 watchdog clock period after 0xa was written. writing to these bits when en is 0 has no effect. these bits are always be read as 0000. enable timer. when a 1 is wri tten to this bit the timer is enabled and starts incrementing. writing a 0 to this bit in timer mode stops the timer. writing a 0 to this bit in watchdog mode has no effect. 0 timer disabled (stop timer) 3 en 0 r/w 1 timer enabled mode select. this bit selects the watchdog timer mode. 0 watchdog mode 2 mode 0 r/w 1 timer mode timer interval select. these bits select the timer interval defined as a given number of 32.768 or 34 khz oscillator periods. 00 clock period x 32768 (typical 1 s) 01 clock period x 8192 (typical 0.25 s) 10 clock period x 512 (typical 15.625 ms) 1:0 int[1:0] 00 r/w 11 clock period x 64 (typical 1.9 ms)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 147 of 252 13.13 usart usart0 and usart1 are serial communications interfaces that can be operated separately in either asynchronous uart mode or in synchronous spi mode. the two usarts have identical function, and are assigned to separate i/o pins. refer to section 13.1 for i/o configuration. 13.13.1 uart mode for asynchronous serial interfaces, the uart mode is provided. in the uart mode the interface uses a two-wire interface consisting of the pins rxd and txd. the uart mode of operation includes the following features: ? 8 or 9 data bits ? odd, even or no parity ? configurable start and stop bit level ? configurable lsb or msb first transfer ? independent receive and transmit interrupts ? independent receive and transmit dma triggers ? parity and framing error status the uart mode provides full duplex asynchronous transfers, and the synchronization of bits in the receiver does not interfere with the transmit function. a uart byte transfer consists of a start bit, eight data bits, an optional ninth data or parity bit, and one or two stop bits. note that the data transferred is referred to as a byte, although the data can actually consist of eight or nine bits. the uart operation is controlled by the usart control and status registers, uxcsr and the uart control register uxucr where x is the usart number, 0 or 1. the uart mode is selected when uxcsr.mode is set to 1. 13.13.1.1 uart transmit a uart transmission is initiated when the usart receive/transmit data buffer, uxdbuf register is written. the byte is transmitted on the txdx output pin. the uxdbuf register is double-buffered. the uxcsr.active bit goes high when the byte transmission starts and low when it ends. when byte transmission ends the uxcsr.tx_byte bit is set. an interrupt request is generated when the uxdbuf register is ready to accept new transmit data. this happens immediately after the transmission has been started, hence a new data byte value can be loaded into the data buffer while a byte is being transmitted. 13.13.1.2 uart receive data reception on the uart is initiated when a 1 is written to the uxcsr.re bit. the uart will then search for a valid start bit on the rxdx input pin and set the uxcsr.active bit high. when a valid start bit has been detected the received byte is shifted into the receive register. the uxcsr.rx_byte bit is set when the operation has completed, and a receive interrupt is generated. at the same time uxcsr.active will go low. the received data byte is available through the uxdbuf register. when uxdbuf is read, uxcsr.rx_byte is cleared by hardware. 13.13.1.3 uart character format if the bit9 and parity bits in register uxucr are set high, parity generation and detection is enabled. the parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and compared to the received ninth bit. if there is a parity error, the uxcsr.err bit is set high. this bit is cleared when uxcsr is read. the number of stop bits to be transmitted is set to one or two bits determined by the register bit uxucr.spb . the receiver will always check for one stop bit. if the first stop bit received during reception is not at the expected stop bit level, a framing error is signaled by setting register bit uxcsr.fe high. uxcsr.fe is cleared when uxcsr is read. the receiver will
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 148 of 252 check both stop bits when uxucr.spb is set. 13.13.2 spi mode this section describes the spi mode of operation for synchronous communication. in spi mode, the usart communicates with an external system through a 3-wire or 4-wire interface. the interface consists of the pins mosi, miso, sck and ssn. refer to section 13.1 for description of how the usart pins are assigned to the i/o pins. the spi mode includes the following features: ? master and slave modes ? configurable sck polarity and phase ? configurable lsb or msb first transfer the spi mode is selected when uxcsr.mode is set to 0. in spi mode, the usart can be configured to operate either as an spi master or as an spi slave by writing the uxcsr.slave bit. 13.13.2.1 spi master operation an spi byte transfer in master mode is initiated when the uxdbuf register is written. the usart generates the sck serial clock using the baud rate generator (see section 13.13.3) and shifts the provided byte from the transmit register onto the mosi output. at the same time the receive register sh ifts in the received byte from the miso input pin. the uxcsr.active bit goes high when the transfer starts and low when the transfer ends. when the transfer ends, the uxcsr.rx_byte and uxcsr.tx_byte bits are set. a receive interrupt is generated when new received data is ready in the uxdbuf usart receive/transmit data register. the polarity and clock phase of the serial clock sck is selected by uxgcr.cpol and uxgcr.cpha as shown in figure 33. the order of the byte transfer is selected by the uxgcr.order bit. at the end of the transfer, the received data byte is available for reading from the uxdbuf register . a transmit interrupt is generated when the unit is ready to accept another data byte for transmission. since uxdbuf is double- buffered, this happens just after the transmission has been initiated. 13.13.2.2 spi slave operation an spi byte transfer in slave mode is controlled by the external system. the data on the mosi input is shifted into the receive register controlled by the serial clock sck which is an input in slave mode. at the same time the byte in the transmit register is shifted out onto the miso output. the uxcsr.active bit goes high when the transfer starts and low when the transfer ends. then the uxcsr.rx_byte and uxcsr.tx_byte bits are set and a receive interrupt is generated. the expected polarity and clock phase of sck is selected by uxgcr.cpol and uxgcr.cpha as shown in figure 33. the expected order of the byte transfer is selected by the uxgcr.order bit. at the end of the transfer, the received data byte is available for reading from the uxdbuf register. the transmit interrupt is generated at the start of the operation. 13.13.2.3 slave select pin (ssn) when the usart is operating in spi mode, configured as an spi slave, the slave select (ssn) pin is an input to the spi. when ssn is held low, the spi slave is active and receives data on the mosi input and outputs data on the miso output. when ssn is held high, the spi slave is inactive and will not receive data. in spi master mode, the ssn pin is not used. when the device operates as an spi master and a slave select signal is needed by an external spi slave device, then a general purpose i/o pin should be used to implement the slave select signal function in software.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 149 of 252 figure 33: spi dataflow 13.13.3 baud rate generation an internal baud rate generator sets the uart baud rate when operating in uart mode and the spi master clock frequency when operating in spi mode. the uxbaud.baud_m[7:0] and uxgcr.baud_e[4:0] registers define the baud rate used for uart transfers and the rate of the serial clock for spi transfers. the baud rate is given by the following equation: f m baud baudrate e baud ? ? + = 28 _ 2 2 ) _ 256 ( where f is the system clock frequency set by the selected system clock source. the register values required for standard baud rates are shown in table 45 for a typical system clock set to 26 mhz. the table also gives the difference in actual baud rate to standard baud rate value as a percentage error. the maximum baud rate for uart mode is f/16 when baud_e is 16 and baud_m is 0, and where f is the system clock frequency. the maximum generated spi clock frequency in master spi mode is f/2 when baud_e is 19 and baud_m is 0, and where f is the system clock frequency. setting higher clock frequencies than this will give erron eous results. the maximum spi bit rate supported in slave mode is f/8.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 150 of 252 baud rate (bps) uxbaud.baud_m uxgcr.baud_e error (%) 2400 131 6 0.04 4800 131 7 0.04 9600 131 8 0.04 14400 34 9 0.13 19200 131 9 0.04 28800 34 10 0.13 38400 131 10 0.04 57600 34 11 0.13 76800 131 11 0.04 115200 34 12 0.13 230400 34 13 0.13 table 45: commonly used baud rate settings for 26 mhz system clock ( CC2510FX ) baud rate (bps) uxbaud.baud_m uxgcr.baud_e error (%) 2400 163 6 0.08 4800 163 7 0.08 9600 163 8 0.09 14400 59 9 0.13 19200 163 9 0.10 28800 59 10 0.14 38400 163 10 0.10 57600 59 11 0.14 76800 163 11 0.10 115200 59 12 0.14 230400 59 13 0.14 table 46: commonly used baud rate settings for 24 mhz system clock ( cc2511fx ) 13.13.4 usart flushing the current operation can be aborted by setting the uxucr.flush register bit. this event will immediately stop the current operation and clear all data buffers. 13.13.5 usart interrupts each usart has two interrupts. these are the rx complete interrupt (urxx) and the tx complete interrupt (utxx). the usart interrupt enable bits are found in the ien0 and ien2 registers. the interrupt flags are located in the tcon and ircon2 registers. refer to section 12.7 on page 49 for details of these registers. the interrupt enables and flags are summarized below. interrupt enables: ? usart0 rx : ien0.urx0ie ? usart1 rx : ien0.urx1ie
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 151 of 252 ? usart0 tx : ien2.utx0ie ? usart1 tx : ien2.utx1ie interrupt flags: ? usart0 rx : tcon.urx0 ? usart1 rx : tcon.urx1 ? usart0 tx : ircon2.utx0 ? usart1 tx : ircon2.utx1 13.13.6 usart dma triggers there are two dma triggers associated with each usart. the dma triggers are activated by rx complete and tx complete events i.e. the same events as the usart interrupt requests. a dma channel can be configured using a usart receive/transmit buffer, uxdbuf , as source or destination address. refer to table 42 on page 90 for an overview of the dma triggers. 13.13.7 usart registers the registers for the usart are described in this section. for each usart there are five registers consisting of the following (x refers to usart number i.e. 0 or 1): ? uxcsr usart x control and status ? uxucr usart x uart control ? uxgcr usart x generic control ? uxdbuf usart x receive/transmit data buffer ? uxbaud usart x baud rate control
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 152 of 252 u0csr (0x86) ? usart 0 control and status bit name reset r/w description usart mode select 0 spi mode 7 mode 0 r/w 1 uart mode uart receiver enable 0 receiver disabled 6 re 0 r/w 1 receiver enabled spi master or slave mode select 0 spi master 5 slave 0 r/w 1 spi slave uart framing error status 0 no framing error detected 4 fe 0 r/w0 1 byte received with incorrect stop bit level uart parity error status 0 no parity error detected 3 err 0 r/w0 1 byte received with parity error receive byte status 0 no byte received 2 rx_byte 0 r/w0 1 received byte ready transmit byte status 0 byte not transmitted 1 tx_byte 0 r/w0 1 last byte written to data b uffer register transmitted usart transmit/receive active status 0 usart idle 0 active 0 r 1 usart busy in transmit or receive mode
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 153 of 252 u0ucr (0xc4) ? usart 0 uart control bit name reset r/w description 7 flush 0 r0/w1 flush unit. when set, this ev ent will immediately stop the current operation and return the unit to idle state. 6 - 0 r/w reserved. must be written as 0. uart data bit 9 contents. this value is used when 9 bit transfer is enabled. when parity is dis abled the value written to d9 is transmitted as the bit 9 when 9 bit data is enabled. if parity is enabled then this bit sets the parity level as follows. 0 even parity 5 d9 0 r/w 1 odd parity uart 9-bit data enable. when this bi t is 1, data is 9 bits and the contents of data bit 9 is given by d9 and parity . 0 8 bits transfer 4 bit9 0 r/w 1 9 bits transfer uart parity enable. 0 parity disabled 3 parity 0 r/w 1 parity enabled uart number of stop bits. selects the number of stop bits to transmit 0 1 stop bit 2 spb 0 r/w 1 2 stop bits uart stop bit level 0 low stop bit 1 stop 1 r/w 1 high stop bit uart start bit level. the polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 low start bit 0 start 0 r/w 1 high start bit
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 154 of 252 u0gcr (0xc5) ? usart 0 generic control bit name reset r/w description spi clock polarity 0 negative clock polarity 7 cpol 0 r/w 1 positive clock polarity spi clock phase 0 data is output on mosi when sck goes from cpol inverted to cpol , and data input is sampled on miso when sck goes from cpol to cpol inverted. 6 cpha 0 r/w 1 data is output on mosi when sck goes from cpol to cpol inverted, and data input is sampled on miso when sck goes from cpol inverted to cpol. bit order for transfers 0 lsb first 5 order 0 r/w 1 msb first 4:0 baud_e[4:0] 0x00 r/w baud rate exponent value. baud_e along with baud_m decides the uart baud rate and the spi master sck clock frequency u0dbuf (0xc1) ? usart 0 receive/transmit data buffer bit name reset r/w description 7:0 data[7:0] 0x00 r/w usart receive and transmit dat a. when writing this register the data written is written to the interna l transmit data register. when reading this register, the data from the internal read data register is read. u0baud (0xc2) ? usart 0 baud rate control bit name reset r/w description 7:0 baud_m[7:0] 0x00 r/w baud rate mantissa value. baud_e along with baud_m decides the uart baud rate and the spi master sck clock frequency
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 155 of 252 u1csr (0xf8) ? usart 1 control and status bit name reset r/w description usart mode select 0 spi mode 7 mode 0 r/w 1 uart mode uart receiver enable 0 receiver disabled 6 re 0 r/w 1 receiver enabled spi master or slave mode select 0 spi master 5 slave 0 r/w 1 spi slave uart framing error status 0 no framing error detected 4 fe 0 r/w0 1 byte received with incorrect stop bit level uart parity error status 0 no parity error detected 3 err 0 r/w0 1 byte received with parity error receive byte status 0 no byte received 2 rx_byte 0 r/w0 1 received byte ready transmit byte status 0 byte not transmitted 1 tx_byte 0 r/w0 1 last byte written to data b uffer register transmitted usart transmit/receive active status 0 usart idle 0 active 0 r 1 usart busy in transmit or receive mode
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 156 of 252 u1ucr (0xfb) ? usart 1 uart control bit name reset r/w description 7 flush 0 r0/w1 flush unit. when set, this ev ent will immediately stop the current operation and return the unit to idle state. 6 - 0 r/w reserved. must be written as 0. uart data bit 9 contents. this va lue is used 9 bit transfer is enabled. when parity is dis abled the value written to d9 is transmitted as the bit 9 when 9 bit data is enabled. if parity is enabled then this bit sets the parity level as follows. 0 even parity 5 d9 0 r/w 1 odd parity uart 9-bit data enable. when this bi t is 1, data is 9 bits and the contents of data bit 9 is given by d9 and parity . 0 8 bits transfer 4 bit9 0 r/w 1 9 bits transfer uart parity enable. 0 parity disabled 3 parity 0 r/w 1 parity enabled uart number of stop bits. selects the number of stop bits to transmit 0 1 stop bit 2 spb 0 r/w 1 2 stop bits uart stop bit level 0 low stop bit 1 stop 1 r/w 1 high stop bit uart start bit level. the polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 low start bit 0 start 0 r/w 1 high start bit
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 157 of 252 u1gcr (0xfc) ? usart 1 generic control bit name reset r/w description spi clock polarity 0 negative clock polarity 7 cpol 0 r/w 1 positive clock polarity spi clock phase 0 data is output on mosi when sck goes from cpol inverted to cpol , and data input is sampled on miso when sck goes from cpol to cpol inverted. 6 cpha 0 r/w 1 data is output on mosi when sck goes from cpol to cpol inverted, and data input is sampled on miso when sck goes from cpol inverted to cpol. bit order for transfers 0 lsb first 5 order 0 r/w 1 msb first 4:0 baud_e[4:0] 0x00 r/w baud rate exponent value. baud_e along with baud_m decides the uart baud rate and the spi master sck clock frequency u1dbuf (0xf9) ? usart 1 receive/transmit data buffer bit name reset r/w description 7:0 data[7:0] 0x00 r/w usart receive and transmit dat a. when writing this register the data written is written to the interna l transmit data register. when reading this register, the data from the internal read data register is read. u1baud (0xfa) ? usart 1 baud rate control bit name reset r/w description 7:0 baud_m[7:0] 0x00 r/w baud rate mantissa value. baud_e along with baud_m decides the uart baud rate and the spi master sck clock frequency
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 158 of 252 13.14 i2s the CC2510FX/cc2511fx provides an industry standard i2s interface. the i2s interface can be used to transfer digital audio samples between the CC2510FX/cc2511fx and an external audio device, eg. audio dac, audio dsp. the i2s interface can be configured to operate as master or slave and may use mono as well as stereo samples. when mono mode is enabled, the same audio sample will be used for both channels. both full and half duplex is supported and automatic -law compression and expansion can be used. the i2s interface consists of 4 signals: ? continous serial clock (sck) ? word select (ws) ? serial data in (rx) ? serial data out (tx) when the module is in master mode, it drives the sck and ws lines. when the i2s interface is in slave mode, these lines are driven by an external master. the data on the serial data lines is transferred most significant bit first with one bit per sck cycle. the ws signal selects the channel of the currently transferred word (left = 0, right = 1). it also determines the length of each word. there is a transition on the ws line one bit time before the first word is transferred and before the last bit of each word. figure 34 shows the i2s signaling. only a single serial data signal is shown in this figure. the sd signal could be the rx or tx signal depending on the direction of the data. the sample in the data buffer is inverted before being sent onto the bus. likewise, the bits received are inverted before they are loaded into the data buffer. sck ws sd msb lsb sample n-1, right channel sample n, left channel sample n+1, right channel msb lsb msb figure 34 i2s digital audio signaling 13.14.1 enabling i2s the i2scfg0.enab bit must be set to enable the i2s transmitter/receiver. however, when i2scfg0.enab is not set, the i2s can still be us ed as a stand-alone -law compression/expansion engine. refer to section 13.14.12 on page 162 for more details about this. 13.14.2 i2s interrupts the i2s has two rx and tx interrupts: ? i2s rx complete interrupt (i2srx) ? i2s tx complete interrupt (i2stx) the i2s interrupt enable bits are found in the i2scfg0 register. the interrupt flags are located in the i2sstat register. the interrupt enables and flags are summarized below. interrupt enables: ? i2s rx: i2scfg0.rxien ? i2s tx: i2scfg0.txien interrupt flags: ? i2s rx: i2sstat.rxirq ? i2s tx: i2sstat.txirq a tx interrupt is generated when the internal tx buffer is empty and the i2s
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 159 of 252 fetches the new data previously written to the i2sdath:i2sdatl registers. the tx interrupt flag, i2sstat.txirq , is cleared when i2sdath register is written. an rx interrupt is generated when the internal rx buffer is full and the contents of the rx buffer is copied to the pair of internal data registers that can be read from the i2sdath:i2sdatl registers. the rx interrupt flag, i2sstat.txirq, is cleared when the i2sdath register is read. notice that interrupts will also be generated if the corresponding rxirq or txirq flags are set from software. the i2s shares inte rrupt vector with usart 1. refer to section 12.7 on page 49 for more details about interrupts. 13.14.3 i2s dma triggers there are two dma triggers associated with the i2s interface. the dma triggers are activated by rx complete and tx complete events, i.e. the same events as the i2s interrupt requests. the dma triggers are not masked by the interrupt enable bits, i2scfg0.rxien and i2scfg0.txien . a dma channel thus can be configured using the i2s receive/transmit data registers, i2sdath:i2sdatl , as source or destination address and use the i2s dma triggers. notice that i2srx / adc_ch6 and i2stx / adc_ch7 dma trigger pairs use the same dma trigger numbers. thus, only one of i2srx and adc_ch6 and one of i2stx and adc_ch7 can be used simultaneously. on the cc2511fx adc channels 7 and 8 cannot be used since p0_6 and p0_7 i/o pins are not available. refer to table 42 on page 90 for an overview of the dma triggers. 13.14.4 underflow/overflow if the i2s attempts to read from the internal tx buffer when it is empty, an underflow condition occurs. the i2s will then continue to read from the data in the tx buffer, and the txunf flag of the i2sstat register will be set. if the i2s attempts to write to the internal rx buffer while it is full, an overflow condition occurs. the contents of the rx buffer will be overwritten and the rxovf flag of the i2sstat register will be set. thus, when debugging an application, software may check for underflow/overflow when an interrupt is generated or when the application completes. the txunf/rxovf flags should be cleared in software. 13.14.5 writing a word (tx) when each sample fits into a single byte or -law compressed samples (always 8 bits) are written, i.e. -law expansion is enabled, only the i2sdath register needs to be written. when each sample is more than 8 bits the low byte must be written to the i2sdatl register before the high byte is written to the i2sdath register. thus, writing the i2sdath register signifies the completion of the write operation. when the i2s is configured to send stereo, i.e. i2scfg0.txmono is 0, the i2sstat.txlr flag can be used to determine whether the left- or right- channel sample is to be written to the data registers. 13.14.6 reading a word (rx) if each sample fits into a single byte or - law compression is enabled, only the i2sdath register needs to be read. when each sample is more than 8 bits the low byte must be read from the i2sdatl register before the high byte is being read from the i2sdath register. thus, reading from the i2sdath register signifies the completion of the read operation. when the i2s is configured to receive stereo, i.e. i2scfg0.rxmono is 0, the i2sstat.rxlr flag can be used to determine whether the sample currently in the data registers is a left- or right-channel sample. 13.14.7 full vs. half duplex the i2s interface supports full duplex and half duplex operation.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 160 of 252 in full duplex both the rx and tx lines will be used. both the i2scfg0.txien and i2scfg0.rxien interrupt enable bits must be set if interrupts are used and both the dma triggers i2stx and i2srx may be used. when half duplex is used only one of the rx and tx lines are typically connected. only the appropriate interrupt flag should be set and only one of the dma triggers should be used. 13.14.8 master mode the i2s is configured as a master device by setting i2scfg0.master to 1. in master mode the sck and ws signals are generated by the i2s. 13.14.8.1 clock generation when the i2s is configured as master, the frequency of the sck clock signal must be set to match the sample rate. the clock frequency must be set before master mode is enabled. sck is generated by dividing the system clock using a fractional clock divider. the amount of division is given by the 15 bit numerator, num and 9-bit denominator, denom as shown in the following formula: ) ( 2 denom num f f clk sck = where 35 . 3 > denom num where f clk is the system clock frequency and f sck is the i2s sck sample clock frequency. the numerator and denominator are set by writing to the clock configuration registers i2sclkf0 , i2sclkf1 and i2sclkf2 . please note that to stay within the timing requirements of the i2s specification [3], a minimum value of 3.35 should be used for the (num / denom) fraction. the fractional divider is made such that most normal sample rates should be supported for most normal word sizes with a 24 mhz system clock frequency ( cc2511fx ). examples of supported configurations for a 24 mhz clk is given in table 47. table 48 shows the configuration values for a 26 mhz system clock frequency. notice that the generated i2s frequency is not exact for the 44.1 khz, 16 bits word size configuration at 26 mhz. the numbers are calculated using the following formulas, where f s is the sample rate and w is the word size: w f f sck s * 2 = s clk f w f denom num clkdiv * * 4 = = f sck (khz) word size (w) clkdiv i2sclkf2 i2sclkf1 i2sclkf0 exact 8 8 93.75 0x01 0x77 0x04 yes 8 16 46.875 0x01 0x77 0x08 yes 44.1 16 8.503401 0x04 0xe2 0x93 yes 48 16 7.8125 0x00 0x7d 0x10 yes table 47 example i2s clock configurations ( cc2511fx , 24 mhz) f sck (khz) word size (w) clkdiv i2sclkf2 i2sclkf1 i2sclkf0 exact 8 8 101.5625 0x06 0x59 0x10 yes 8 16 50.78125 0x06 0x59 0x20 yes
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 161 of 252 44.1 16 9.21201 0x8a 0x2f 0x1b no 48 16 8.46354 0x06 0x59 0xc0 yes table 48 example i2s clock configurations ( CC2510FX , 26 mhz) 13.14.8.2 word size the word size must be set before master mode is enabled. the word size is the number of bits used for each sample and can be set to a value between 1 and 33. to set the word size, write word size ? 1 to the i2scfg.words[4:0] bits. setting the word size to a value of 17 or more causes the i2s to pad each word with 0?s in the least significant bits since the data registers provide maxmum 16 bits. this feature allows samples to be sent to an i2s device that takes a higher resolution than 16 bits. if the size of received samples exceeds 16 bits, only the 16 most significant bits will be put in the data registers and the remaining low order bits will be discarded. 13.14.9 slave mode the i2s is configured as a slave device by setting i2scfg0.master to 0. when in slave mode the sck and ws signals are generated by an external i2s master and are inputs to the i2s interface. 13.14.9.1 word size when the i2s operates in slave mode, the word size is determined by the master that generates the ws signal. the i2s will provide bits from the internal 16-bit buffer until the buffer is empty. if the buffer becomes empty and the master still requests more bits, the i2s will send 0?s (low order bits). if more than 16 bits are being received, the low order bits are discarded. 13.14.10 mono the i2s also supports mono audio samples. to receive mono samples, set the i2scfg0.rxmono bit to 1. words from the right channel will then not be read into the data registers. this feature is included because some mono devices repeat their audio data in both channels and the left channel is the default mono channel. to send mono samples, set the i2scfg0.txmono bit to 1. each word will then be repeated in both channels before a new word is fetched from the data registers. this is to enable sending a mono audio signal to a stereo audio sink device. 13.14.11 word counter the i2s contains a 10-bit word counter that counts the number of transitions on the ws line since the last time the word counter was cleared. triggers are used to clear the word counter. when a trigger occurs or software writes any value to the i2swcnt register, the current value of the word counter is copied into the wcnt[9:0] field in the i2swcnt/i2sstat registers and the word counter is cleared. three triggers can be used to copy/clear the word counter. ? usb sof: usb start of frame. occurs every ms. ? t1_ch0: timer 1, compare, channel 0 ? ioc_1: io pin input transition when the i2s is configured not to use any trigger, the word counter can only be copied/cleared from software. the i2scfg1.trignum[1:0] field selects the trigger source. the word counter will sa turate if it reaches its maximum value. software should configure the trigger-interval and sample- rate to ensure this never happens. cc2511fx: the word counter is typically used to calculate the average sample rate over a long period of time (e.g. 1 second) needed by adaptive isochronous usb endpoints. the usb sof event must then be used as trigger.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 162 of 252 13.14.12 -law compression and expansion the i2s interface can be configured to perform -law compression and expansion. -law compression is enabled by setting the i2scfg0.ulawc bit to 1 and -law expansion is enabled by setting the i2scfg0.ulawe bit to 1. when the i2s interface is enabled, i.e. the i2scfg0.enab bit is 1, and -law expansion is enabled, every byte of -law compressed data written to the i2sdath register is expanded to a 16-bit sample before being transmitted. when the i2s interface is enabled and -law compression is enabled each sample received is compressed to an 8-bit -law sample and put in the i2sdath register. when the i2s interface is disabled, i.e. the i2scfg0.enab bit is 0, it can still be used to perform -law compression/expansion for other resources in the system. to perform an expansion, the i2scfg0.ulawe must be set and the i2scfg0.ulawc bit must be cleared. then write a byte of compressed data to the i2sdath register. the expansion takes one clock cycle to perform, and then the result can be read from the i2sdath:i2sdatl registers. to perform a compression the i2scfg0.ulawc bit must be set and the i2scfg0.ulawe bit must be cleared. to start the compression, write a uncompressed 16-bit sample to the i2sdath:i2sdatl registers. the compression takes one clock cycle to perform, and then the result can be read from the i2sdath register. only one of the flags i2scfg0.ulawc and i2scfg0.ulawe should be set when the i2s interface is used without the i2scfg0.enab bit is set. 13.14.13 i2s registers this section describes all i2s registers used for control and status for the i2s. the usb registers reside in xdata memory space in the region 0xdf40-0xdf48. table 49 gives an overview of register addresses while the remaining tables in this section describe each register. notice that the reset values for the registers reflect a configuration with 16-bit stereo samples and 44.1 khz sample rate. the i2s is not enabled at reset. xdata address register description 0xdf40 i2scfg0 i2s configuration register 0 0xdf41 i2scfg1 i2s configuration register 1 0xdf42 i2sdatl i2s data low byte 0xdf43 i2sdath i2s data high byte 0xdf44 i2swcnt i2s word count register 0xdf45 i2sstat i2s status register 0xdf46 i2sclkf0 i2s clock configuration register 0 0xdf47 i2sclkf1 i2s clock configuration register 1 0xdf48 i2sclkf2 i2s clock configuration register 2 table 49 overview of i2s registers 0xdf40: i2scfg0 ? i2s configuration register 0 bit field name reset r/w description transmit interrupt enable. 7 txien 0 r/w 0 interrupts are disabled
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 163 of 252 bit field name reset r/w description 1 interrupts are enabled receive interrupt enable. 0 interrupts are disabled 6 rxien 0 r/w 1 interrupts are enabled 5 ulawe 0 r/w -law expansion enable bit. set to enable expansion of data to transmit when enab is set, or to expand data written to i2sdath when enab is cleared. 4 ulawc 0 r/w -law compression enable bit. set to enable compression of data received when enab is set, or to compress data written to i2sdath:i2sdatl when enab is cleared. 3 txmono 0 r/w tx mono enable. if this bit is set, each sample of audio data will be repeated in both channels before a new sample is fetched. this is to enable sending a mono signal to a ster eo audio sink device. 2 rxmono 0 r/w rx mono enable. if this bit is set, data from the right channel will be discarded, i.e. not be read into the data registers. this feature is included because some mono devices repeat their audio data in both channels and left is the default mono channel. 1 master 0 r/w the master bit indi cates if the i2s should generate the clk and ws signals or if it should read them from the pads. 0 enab 0 r/w the bit enables the i2s interface. notice that this bit must not be set if the i2s is to be used as a -law compression/expansion unit. 0xdf41: i2scfg1 ? i2s configuration register 1 bit field name reset r/w description 7:3 words[4:0] 0x0f r/w this field gives the word size ? 1. the word size is the bit-length of one sample for one channel. used to generate the ws signal when in master mode. reset value 0x0f give 15 + 1 = 16 bit samples. 2:1 trignum[1:0] 00 r/w word counter copy and clear trigger to use. when zero, the word counter can only be cleared by software. 0 ? no trigger 1 ? usb sof 2 ? ioc_1 3 ? t1_ch0 0 ioloc 0 r/w the pin locations for the i2s signals. this bit selects between the two alternavie pin mapping alternatives. refer to table 41 for an overview of pin locations. 0 ? alt. 1 in table 41 is used 1 ? alt. 2 in table 41 is used 0xdf42: i2sdatl ? i2s data low byte bit field name reset r/w description
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 164 of 252 bit field name reset r/w description 7:0 i2sdat[7:0] 0x00 r/w data register low byte. if the i2sdatl register is not written between two writes of the i2sdath register, the low byte of the tx register will be cleared. 0xdf43: i2sdath ? i2s data high byte bit field name reset r/w description 7:0 i2sdat[15:8] 0x00 r/w data register high byte. when this register is read, the rxirq bit of the i2sstat register is cleared and the rx buffer is considered empty. when this register is written, the txirq bit of the i2sstat register is cleared and the tx buffer is considered full. 0xdf44: i2swcnt ? i2s word count register bit field name reset r/w description 7:0 wcnt[7:0] 0x00 r/w this register contains the 8 low order bits of the 10- bit nternal word counter at the time the last trigger specified by i2scfg1.trignum occurred. if this register is written (any value), the value of the internal word counter is c opied into this register and the internal word counter is cleared. refer to section 13.14.11 for details about how to use this register. 0xdf45: i2sstat ? i2s status register bit field name reset r/w description 7 txunf 0 r/w tx buffer underflow. this bit must be cleared by software. 6 rxovf 0 r/w rx buffer overflow. this bit must be cleared by software. 5 txlr 0 r left (=0) or right (=1) channel should be placed in transmit buffer. 4 rxlr 0 r left (=0) or right (=1) channel currently in receive buffer. 3 txirq 0 r/w h0 interrupt flag indicating that a tx interrupt request has not been serviced. this bit is cleared by hardware when the i2sdath register is written. 2 rxirq 0 r/w h0 interrupt flag indicating that an rx interrupt request has not been serviced. this is cleared by hardware when the i2sdath register is read. 1:0 wcnt[9:8] 00 r upper 2 bits of the copy of the 10-bit internal word counter at the time of the last trigger.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 165 of 252 0xdf46: i2sclkf0 ? i2s clock configuration register 0 bit field name reset r/w description 7:0 denom[7:0] 0x93 r/w the clock division denominator low bits 0xdf47: i2sclkf1 ? i2s clock configuration register 1 bit field name reset r/w description 7:0 num[7:0] 0xe2 r/w clock division numerator low bits 0xdf48: i2sclkf2 ? i2s clock configuration register 2 bit field name reset r/w description 7 denom[8] 0 r/w clock division denominator high bits 6:0 num[14:8] 0x04 r/w clock division numerator high bits.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 166 of 252 13.15 usb controller note: the usb controller is only available on the cc2511fx . the cc2511fx contains a full-speed usb 2.0 compatible function controller for serial communication with a pc or other equipment with usb host functionality. note: this section w ill focus on describing the functionality of the usb controller. thus, it is assumed that the reader has a good understanding of usb and is familiar with the terms and concepts used. refer to the universal serial bus specification for details. standard usb nomenclature is used regaring in and out. i.e, in is always into the host (pc) and out is out of the host (into cc2511fx) the usb controller monitors the usb bus for relevant activity and handles packet transfer. the usb f unction will always operate as a slave on the usb bus. a packet can therefore only be sent (or received) when the usb host sends a request in the form of a token. appropriate response to usb interrupts and loading/unloading of packets into/from endpoint fifos is the responsibility of the firmware. the firmware must be able to reply correctly to all standard requests from the usb host and work according to the protocol implemented in the driver on the pc. the usb controller has the following features: ? full-speed operation (up to 12 mbps) ? 5 endpoints (in addition to endpoint 0) that can be used as in, out or in/out and can be configured as bulk, interrupt or isochronous. ? 1 kb sram fifo available for storing usb packets ? endpoints supporting packet sizes from 8 ? 512 bytes ? support for double buffering of usb packets figure 35 shows a block diagram of the usb controller. the usb phy is the physical interface with input and output drivers. the usb sie is the serial interface engine which controls the packet transfer to/from the endpoints. the usb controller is connected to the rest of the system through the memory arbiter. usb phy dp dm ep0 ep1 ep2 ep3 ep4 ep5 usb controller usb sie 1 kb sram (fifos) memory arbiter figure 35: usb controller block diagram
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 167 of 252 13.15.1 usb registers the operation of the usb is configured through a set of usb registers. these usb registers are mapped to xdata memory space as shown in figure 10 on page 36. in addition to configuration registers, the usb registers also provide status information. the usb registers control/status bits are referred to where appropriate in the following sections while section 13.15.11 on page 175 gives a full description of all usb registers. 13.15.2 48 mhz clock a 48 mhz external crystal must be used for the usb controller to operate correctly. this 48 mhz clock is divided by two internally to generate the system clock at 24 mhz. it is important that the crystal oscillator is stable before the usb controller is accessed. see 13.10.3 for details on how to set up the crystal oscillator. 13.15.3 usb enable the usb controller must be enabled before it is used. this is performed by setting the sleep.usb_en bit to 1. setting sleep.usb_en to 0 will reset the usb controller. 13.15.4 usb interrupts there are 3 interrupt flag registers with associated interrupt enable mask registers. the usbcif register contains flags for common usb interrupts. the usbiif register has interrupt flags for endpoint 0 and all the in endpoints. usboif has interrupt flags for all out endpoints. all interrupts except sof and and suspend are initially enabled after reset. when the interrupt flag of an enabled interrupt is set, the usb interrupt is asserted. this interrupts the 8051 cpu which will start executing the interrupt service routine if there is no higher priority interrupts pending. the usb controller uses interrupt number 6 for usb interrupts. this is the same interrupt number used for port 2 inputs. thus, the interrupt routine must also handle port 2 interrupts if they are used. the interrupt routine should read all the interrupt flag registers and take action depending on the status of the flags. the interrupt flag registers will be cleared when they are read. the interrupt flags must therefore be saved in memory (typically in a local variable on the stack) to be used in multiple operations. to enable usb interrupts ien2.p2ie must be set to 1. it is important that the p2ifg register is cleared and then the ircon2.p2if bit is cleared at the end of the usb interrupt service routine after the interrupt flags have been read. this allows new usb/p2 interrupts to be detected. refer to table 33 for a complete list of interrupts and section 12.7 for more details about interrupts. 13.15.4.1 usb resume interrupt bit 7 of port 0 is used to wake up the cc2511fx from pm1/suspend when resume signaling has been detected on the usb bus. ien1.p0ie must therefore be set to 1 to enable p0 interrupts. pictl.p0ienh must be set to 1 to enable interrupts on p0[7:4] and pictl.p0icon must be 0 to enable interrupts on rising edge. the p0 interrupt routine should check bit 7 of p0ifg and resume if this bit is set. notice that bit 7 and bit 6 of port 0 are not available as external ports on cc2511fx . if pm1 is entered from within an interrupt routine (typically the usb/p2 interrupt routine) due to a susp end interrupt, it is important that the priority of the p0 interrupt is set higher than the interrupt that entered pm1. see section 13.15.9 for more details about suspend and resume. 13.15.5 endpoint 0 endpoint 0 (ep0) is a bi-directional control endpoint. a usb function is required to implement a control endpoint at endpoint 0. during the enumeration phase all communication is performed across this endpoint. before the usbaddr register has been set (to a value other than 0), the usb controller will only be able to communicate through endpoint 0. setting the usbaddr register will bring the usb function out of the default state in the enumeration phase and into the
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 168 of 252 addressed state. all configured endpoints will then be available for the application. the ep0 fifo is only used as in or out at a time. the maximum packet size for endpoint 0 is fixed at 32 bytes. double buffering is not provided for endpoint 0. endpoint 0 is controlled through the usbcs0 register. the usbindex register must be set to 0. the usbcnt0 register contains the number of bytes received. 13.15.5.1 interrupts endpoint 0 will generate an interrupt on any of the following events: ? a data packet has been received. ? a data packet that was loaded into the ep0 fifo has been sent to the usb host. ? an in transaction has been completed. ? the usbcs0.sent_stall bit has been set. ? the usbcs0.setup_end bit has been set. 13.15.5.2 error conditions when a protocol error occurs the usb controller sends a stall handshake. the usbcs0.sent_stall bit is set and an interrupt is generated. a protocol error can be any of the following: ? an out token is received after usbcs0.data_end has been set to complete the out data stage. thus, the host tries to send more data than expected. ? an in token is received after usbcs0.data_end has been set to complete the in data stage. thus, the host tries to receive more data than expected. ? the usb host tries to send a packet that exceeds the maximum packet size during the out data stage. ? the size of the data1 packet received during the status stage is not 0. the firmware can also terminate the current transaction by setting the usbcs0.send_stall bit. the usb controller will then send stall handshake in response to requests from the usb host. when firmware receives an ep0 interrupt and finds that the usbcs0.sent_stall bit is set it should clear the usbcs0.sent_stall bit and abort the current transfer. if ep0 receives an unexpected token during the data stage usbcs0.setup_end will be set and an ep0 interrupt will be generated. ep0 will then switch to the idle state. firmware should then set the usbcs0.clr_setup_end bit and abort the current transfer. if usbcs0.outpkt_rdy is set, this indicates that another setup packet has been received that firmware should process. 13.15.5.3 setup transactions (idle state) the first transaction in a control transfer consists of a setup packet, sent from the host. a setup packet is always 8 bytes and contains a pre-defined set of fields. this is the setup stage of a control transfer and ep0 will be in the idle state. consult the usb 2.0 specification [2] for details about this. t he usb controller will reject the first packet if the size of the packet is not 8 bytes. also, the usb controller will examine the contents of the setup packet to determine whether the data stage will consist of in or out transactions and ep 0 will switch state to tx or rx when the usbcs0.clr_outpkt_rdy bit is set if usbcs0.data_end is not set. when a packet is received, the usbcs0.outpkt_rdy bit will be set and an ep0 interrupt is generated. firmware should perform the follwing when a setup packet has been received: 1. unload the setup packet from the ep0 fifo 2. examine the contents and perform the appropriate operations
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 169 of 252 3. set the usbcs0.clr_outpkt_rdy bit. this denotes the end of the setup stage. if the control transfer has no data stage, the usbcs0.data_end bit must also be set. if there is no data stage, the usb controller will stay in the idle state. 13.15.5.4 in transactions (tx state) if the control transfer requires data to be sent to the host, the setup stage will be followed by one or more in transactions (a data in stage). in this case the usb controller will be in tx state and only accept in tokens. if more than 32 bytes (maximum packet size) is to be sent, the data must be split into a number of 32 byte packets followed by a residual packet. if the number of bytes to send is divisible by 32, the residual packet will be a zero length data packet. thus, a packet size less than 32 bytes denotes the end of the transfer. firmware should load the ep0 fifo with the first data packet and set the usbcs0.inpkt_rdy bit as soon as possible after the usbcs0.clr_outpkt_rdy bit has been set. the usbcs0.inpkt_rdy bit will be cleared and an ep0 interrupt will be generated when the data packet has been sent. firmware might then load more data packets as necessary. an ep0 interrupt will be generated for each packet sent. firmware must set usbcs0.data_end in addition to usbcs0.inpkt_rdy when the last data packet has been loaded. this will start the status stage of the control transfer. ep0 will switch to the idle state when the status stage has comp leted. the status stage may fail if the usbcs0.send_stall bit is set. the usbcs0.sent_stall bit will then be set and an interrupt will be generated as explained in section 13.15.5.2. if usbcs0.inpkt_rdy is not set when receiving an in token, the usb controller will reply with a nak to indicate that the endpoint is working, but temporarily has no data to send. 13.15.5.5 out transactions (rx state) if the control transfer requires data to be received from the host, the setup stage will be followed by one or more out transactions (a data out stage). in this case the usb controller will be in rx state and only accept out tokens. if more than 32 bytes (maximum packet size) is to be received, the data must be split into a number of 32 byte packets followed by a residual packet. if the number of bytes is divisible by 32, the residual packet will be a zero length data packet. thus, a packet size less than 32 bytes denotes the end of the transfer. the usbcs0.outpkt_rdy bit will be set and an ep0 interrupt will be generated when a data packet has been received. the firmware should set usbcs0.clr_outpkt_rdy when the data packet has been unloaded from the ep0 fifo. when the last data packet has been received (packet size less than 32) firmware should also set usbcs0.data_end . this will start the status stage of the control transfer. ep0 will switch to the idle state when the status stage has completed. the status stage may fail if the data1 packet received is not a zero length data packet or the usbcs0.send_stall bit is set. the usbcs0.sent_stall bit will then be set and an interrupt will be generated as explained in section 13.15.5.2. 13.15.6 endpoints 1 ? 5 each endpoint can be used as a in only, out only or in/out. for a in/out endpoint there are basically two endpoints, a in and a out endpoint assiociated with the endpoint number. configuration and control of in endpoints is performed by accessing the usbcsil and usbcsih registers. the usbcsol and usbcsoh registers are used to configure and control out endpoints. each in and out endpoint can be configured as a isochronous or bulk/interrupt endpoint. this is done by setting the usbcsih.iso and usbcsoh.iso bits. bulk and interrupt endpoints are handled identically by the usb controller but will have different properties from a firmware perspective.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 170 of 252 the usbindex register must have the value of the endpoint number before the indexed endpoint registers are accessed. 13.15.6.1 fifo management each endpoint has a number of fifo memory bytes available for incoming and outgoing data packets. table 50 shows the fifo size for endpoints 1 ? 5. it is the firmware that is responsible for setting the usbmaxi and usbmaxo registers correctly for each endpoint so that no data potentially gets overwritten. when both the in and out endpoint of an endpoint number do not use double buffering, the sum of usbmaxi and usbmaxo must not exceed the fifo size for the endpoint. figure 36 a) shows how the in and out fifo memory for an endpoint is organized with single buffering. the in fifo grows down from the top of the endpoint memory region while the out fifo grows up from the bottom of the endpoint memory region. when the in or out endpoint of an endpoint number use double buffering, the sum of usbmaxi and usbmaxo must not exceed half the fifo size for the endpoint. figure 36 b) illustrates the in and out fifo memory for an endpoint that uses double buffering. notice that the second out buffer starts from the middle of the memory region and grows upwards. the second in buffer also starts from the middle of the memory region but grows downwards. to configure an endpoint as in only, set usbmaxo to 0 and to configure an endpoint as out only, set usbmaxi to 0. the usbmaxo and usbmaxi registers should be 0 for unused endpoints. ep number fifo size (in bytes) 1 32 2 64 3 128 4 256 5 512 table 50 fifo sizes for ep 1 ? 5 figure 36: in/out fifos, a) double buffering b) single buffering
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 171 of 252 13.15.6.2 double buffering double buffering allows two packets to be buffered in the fifo. this reduces retransmission and is highly recommended for isochronous endpoints which do not use retransmission. for isochronous endpoint one data packet will be sent/received every usb frame. however, the data packet may be sent/received at any time during the usb frame period. thus, two data packets may be sent/received at a few micro seconds interval. for isochronous endpoints an incoming packet will be lost if there is no buffer available and a zero length data packet will be sent if there is no data packet ready for transmission when the usb host requests data. double buffering is not as critical for bulk and interrupt endpoints since packets will not be lost. double buffering, however, may improve the effective data rate for bulk endpoints. to enable double buffering for an in endpoint, set usbcsih.in_dbl_buf to 1. to enable double buffering for an out endpoint, set usbcsoh.out_dbl_buf to 1. 13.15.6.3 fifo access the endpoint fifos are accessed by reading and writing to the registers in table 53. writing to a register causes the byte written to be in serted into the in fifo. reading a register causes the next byte in the out fifo to be extracted and the value of this byte to be returned. when a data packet has been written to a in fifo the usbcsil.inpkt_rdy bit must be set. if double buffering is enabled, the usbcsil.inpkt_rdy bit will be cleared immediately after it has been written and another data packet can be loaded. this will not generate an interrupt, since an interrupt is only generated when a packet has been sent. when double buffering is used firmware should check the status of the usbcsil.pkt_present bit before writing to the in fifo. if this bit is 0, two data packets can be written. double buffered isochronous endpoints should only need to load two packets the first time the in fifo is loaded. after that, one packet is loaded for every usb frame. to send a zero length data packet set usbcsil.inpkt_rdy without loading a data packet into the in fifo. a data packet can be read from the out fifo when the usbcsol.outpkt_rdy bit is set. an interrupt will be generated when this occurs, if enabled. the size of the data packet is kept in the usbcnth:usbcntl registers. when the data packet has been read from the out fifo, the usbcsol.outpkt_rdy bit must be cleared. if double buffering is enabled there may be two data packets in the fifo. if another data packet is ready when the usbcsol.outpkt_rdy bit is cleared the usbcsol.outpkt_rdy bit will be set immediately and an interrupt will be generated to signal that a new data packet has been received. the usbcsol.fifo_full bit will be set when there are two data packets in the out fifo. the autoclear feature is supported for out endpoints. when enabled, the usbcsol.outpkt_rdy bit is cleared automatically when usbmaxo bytes have been read from th e out fifo. the autoclear feature is enabled by setting the usbcsoh.autoclear bit. the autoclear feature can be used to reduce the time the data packet occupies the out fifo buffer and is typically used for bulk endpoints. a complementary autoset feature is also supported for in endpoints. when enabled, the usbcsil.inpkt_rdy bit is set automatically when usbmaxi bytes have been written to the in fifo. the autoset feature is enabled by setting the usbcsoh.autoset bit. the autoset feature can reduce the overall time it takes to send a data packet and is typically used for bulk endpoints. 13.15.6.4 endpoint interrupts in endpoints generate interrupts by setting the interrupt flags in the usbiif register in the following situations: ? a data packet has been successfully sent to the host. ? a stall condition has been generated by the hardware. ? the in fifo is flushed due to the usbcsih.flush_packet bit being set.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 172 of 252 out endpoints generate interrupts by setting the interrupt flags in the usboif register in the following situations: ? a data packet has been received. usbcsol.outpkt_rdy has been set. ? a stall condition has been generated by the hardware. 13.15.6.5 bulk/interrupt in endpoint interrupt in transfers occur at regular intervals while bulk in transfers utilize available bandwidth not allocated to isochronous, interrupt and control transfers and can happen at any time. interrupt in endpoints may set the usbcsih.frc_data_tog bit. when this bit is set the data toggle bit is continuously toggled regardless of whether an ack was received. this feature is typically used by interrupt in endpoints that report rate feedback for isochronous endpoints. a bulk/interrupt in endpoint can be stalled by setting the usbcsil.send_stall bit to 1. when the endpoint is stalled the usb controller will respond with a stall handshake to in tokens. the usbcsil.sent_stall bit will then be set and an interrupt will be generated. a bulk transfer longer than the maximum packet size is performed by splitting the transfer into a number of data packets of maximum size followed by a smaller data packet containing the remaining bytes. if the transfer length is divisible by the maximum packet size a zero length data packet is sent last. thus, a packet with a size less than the maximum packet size denotes the end of the transfer. the autoset feature can be useful in this case, since many data packets will be of maximum size. 13.15.6.6 isochronous in endpoint an isochronous in endpoint is guaranteed to be able to send exactly one data packet every usb frame and is typically used to send a continous stream of data. if there is no data packet loaded in the in fifo when the usb host requests data, the usb controller sends a zero length data packet. the usbcsil.underrun bit will be set and an interrupt will be generated. double buffering requires the data packet to be loaded during the frame before the packet is sent. if the first data packet is loaded before an in token is received the data packet will be sent during the same frame the packet is loaded which violates the double buffering strategy. thus, when double buffering is used, the usbpow.iso_wait_sof bit should be set to avoid this. setting this bit will ensure that a loaded data packet is not sent until the next sof token has been received. the autoset feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame to match the source data rate. notice that an isochronous endpoint cannot be stalled. 13.15.6.7 bulk/interrupt out endpoint interrupt out transfers occur at regular intervals while bulk out transfers utilize available bandwidth not allocated to isochronous, interrupt and control transfers and can happen at any time. a bulk/interrupt out endpoint can be stalled by setting the usbcsol.send_stall bit to 1. when the endpoint is stalled the usb controller will respond with a stall handshake when the host is done sending the data packet. the data packet is discarded and is not placed in the out fifo. the usb controller will set the usbcsol.sent_stall bit and generate an interrupt when the stall handshake is sent. as the autoset feature is useful for bulk in endpoints, the autoclear feature is useful for out endpoint since many packets will be of maximum size. 13.15.6.8 isochronous out endpoint an isochronous out endpoint is guaranteed to receive exactly one data packet every usb frame and is typically used to receive a continous stream of data. if there is no buffer available when a data packet is being received the
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 173 of 252 usbcsol.overrun is set and the packet data will be lost. firmware can reduce the chance for this to happen by using double buffering and use dma to effectively unload data packets. an isochronous data packet in the out fifo may have bit errors. the hardware will detect this condition and set usbcsol.data_error . firmware should therefore always check this bit when unloading a data packet. the autoclear feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame to match the source data rate. notice that an isochronous endpoint cannot be stalled. 13.15.7 dma dma should be used to fill the in endpoint fifos and empty the out endpoint fifos. using dma will improve read/write performance significantly compared to using the 8051 cpu. it is therefore highly recommended to use dma unless timing is not critical or only a few bytes are to be transferred. there are no dma triggers for the usb controller. thus, dma transfers must be triggered by firmware. the dma transfer mode should be set to block transfer. the word size can be byte (8 bits) or word (16 bits). when word size transfer is used the endian register must be set correctly. the endian.usbrle bit selects whether word data is read as little or big endian from out fifos and the endian.usbwle bit selects whether word data is written as little or big endian to in fifos. writing and reading words for the different settings is shown in figure 37 and figure 38 respectively. notice that the setting for these bits will be used for all endpoints. consequently, it is not possible to have multiple dma channels active at once that use different endianness. the endian register must be configured to use big endian for both read and write for a word size transfer to produce the same result as a byte size transfer of an even number of bytes. refer to section 12.12 for more information about the endian register. word size transfer is slightly more efficient than byte transfer. refer to section 13.2 for more information about how to use dma. msb lsb msb lsb msb lsb msb lsb sync pid crc16 eop msb lsb lsb msb lsb msb lsb msb sync pid crc16 eop to host to host figure 37 writing little/big endian
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 174 of 252 figure 38 reading little/big endian 13.15.8 usb reset a usb hub may signal reset at any time. when reset signaling is detected on the bus, the usb controller will set usbcif.rstif and generate an interrupt if usbcie.rstie is set. the firmware should take appropriate action when a usb reset occurs. a usb reset would normally cause the system to be initialized to a known reset state. the usb function will typically be reset one or more times during the enumeration phase right after the usb cable is connected. a usb reset places the device in the default state. in this state the device will only respond to address 0 (the default address). the following actions are performed by the usb controller when a usb reset occurs: ? usbaddr is set to 0 ? usbindex is set to 0 ? all endpoint fifos are flushed ? e0csr , usbcsil , usbcsih , usbcsol , usbcsoh are cleared. ? all interrupts, except suspend, are enabled ? an interrupt is generated thus, firmware should close all pipes and wait for a new enumeration phase when usb reset is detected. 13.15.9 suspend and resume the usb controller will enter suspend mode when the usb bus has been continuously idle for 3 ms. an interrupt will be generated if t he usbcie.suspendie is set. while in suspend mode, only limited current can be sourced from the usb bus. see the usb 2.0 specification [2] for details about this. to be able to meet the suspend current requirement, the cc2511fx should be taken down to pm1 when suspend is detected. the cc2511fx should not enter pm2 or pm3 since this will reset the usb controller. any valid non-idle signaling on the usb bus will cause the usb resume interrupt to be generated and wake up the system if the usb resume interrupt is configured correctly. refer to 13.15.4.1 for details about how to set up the usb resume interrupt. when the system wakes up (enters pm0) from suspend no usb registers must be accessed before xosc has stabilized. be aware that the u sb controller will stay in suspend mode until xosc has stabilized and non-idle signaling is detected on the usb bus. the usbcif.resumeif interrupt flag will be set and a usb interrupt will be generated if enabled when the usb controller exits from suspend mode. usb reset will also wake up the system from suspend. the usb resume interrupt will be genera ted, but the usbcif.rstif interrupt flag will be set instead of the usbcif.resumeif interrupt flag. 13.15.10 remote wakeup the usb controller can resume from suspend by signaling resume to the usb hub. resume is performed by setting usbpow.resume to 1 for approximately 10 ms. according to the usb 2.0 specification, the resume signaling must be present for at least 1 ms and no more
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 175 of 252 than 15 ms. it is, however, recommended to keep the resume signaling for approximately 10 ms. notice that the device must report back to the usb host that it supports remote wakeup when the host sends the get_status standard device request. 13.15.11 usb registers this section describes all usb registers used for control and status for the usb. the usb registers reside in xdata memory space in the region 0xde00- 0xde3f. these registers can be divided into three groups: the common usb registers, the indexed endpoint registers and the endpoint fifo registers. overview of common usb registers. table 51, table 52 and table 53 give an overview of register addresses for each of the three groups respectively while the remaining tables in this section describe each register. the indexed endpoint registers represent the currently selected endpoint. the usbindex register is used to select the endpoint. notice that the upper register addresses 0xde2c ? 0xde3f are reserved. xdata address register description 0xde00 usbaddr function address 0xde01 usbpow power/control register 0xde02 usbiif in endpoints and ep0 interrupt flags 0xde03 - reserved 0xde04 usboif out endpoints interrupt flags 0xde05 - reserved 0xde06 usbcif common usb interrupt flags 0xde07 usbiie in endpoints and ep0 interrupt enable mask 0xde08 - reserved 0xde09 usboie out endpoints interrupt enable mask 0xde0a - reserved 0xde0b usbcie common usb interrupt enable mask 0xde0c usbfrml current frame number (low byte) 0xde0d usbfrmh current frame number (high byte) 0xde0e usbindex selects current endpoint. make sure this register has the value of the endpoint before any of the registers in table 52 are accessed. this register must be set to a value in the range 0 ? 5. table 51 overview of common usb registers xdata address register description valid usbindex value(s) 0xde10 usbmaxi max. packet size for in endpoint 1 ? 5 usbcs0 ep0 control and status (usbindex = 0) 0 0xde11 usbcsil in ep{1-5} control and status low 1 ? 5 0xde12 usbcsih in ep{1-5} control and status high 1 ? 5 0xde13 usbmaxo max. packet size for out endpoint 1 ? 5 0xde14 usbcsol out ep{1-5} control and status low 1 ? 5 0xde15 usbcsoh out ep{1-5} control and status high 1 ? 5 usbcnt0 number of received bytes in ep0 fifo (usbindex = 0) 0 0xde16 usbcntl number of bytes in out fifo low 1 ? 5 0xde17 usbcnth number of bytes in out fifo high 1 ? 5 table 52 overview of indexed endpoint registers
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 176 of 252 xdata address register description 0xde20 usbf0 endpoint 0 fifo 0xde22 usbf1 endpoint 1 fifo 0xde24 usbf2 endpoint 2 fifo 0xde26 usbf3 endpoint 3 fifo 0xde28 usbf4 endpoint 4 fifo 0xde2a usbf5 endpoint 5 fifo table 53 overview of endpoint fifo registers 0xde00: usbaddr ? function address bit field name reset r/w description 7 update 0 r0 this bit is set w hen the usbaddr register is written and cleared when the address becomes effective. 6:0 usbaddr[6:0] 0x00 r/w function address. 0xde01: usbpow ? power/control register bit field name reset r/w description 7 iso_wait_sof 0 r/w when this bit is set the usb controller will only send zero length data packets from the time inpktrdy is set and until the first sof token has been received. this only applies to isochronous endpoints . 6:4 - 000 r0 unused 3 rst 0 r during reset si gnaling, this bit is set. 2 resume 0 r/w drive resume signaling for remote wakeup. according to the usb specification the duration of driving resume must be at least 1 ms and no more than 15 ms. it is recommended to keep this bit set for approximately 10 ms. this bit must not be set until the usb controller has been in suspend mode for at least 2 ms. 1 suspend 0 r suspend mode entered. this bit will only be used when suspend_en is set. reading the usbcif register or setting resume will clear this bit. 0 suspend_en 0 r/w suspend detection enable. when this bit is set, the usbcif.suspend will be set when the usb bus has been idle for 3 ms. an interrupt will also be generated, if usbcie.suspend is set. 0xde02: usbiif ? in endpoints and ep0 interrupt flags bit field name reset r/w description 7:6 - 00 r0 unused 5 inep5if 0 r interrupt flag for in endpoint 5
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 177 of 252 bit field name reset r/w description 4 inep4if 0 r interrupt flag for in endpoint 4 3 inep3if 0 r interrupt flag for in endpoint 3 2 inep2if 0 r interrupt flag for in endpoint 2 1 inep1if 0 r interrupt flag for in endpoint 1 0 ep0if 0 r interrupt flag for endpoint 0 0xde04: usboif ? out endpoints interrupt flags bit field name reset r/w description 7:6 - 00 r0 unused 5 outep5if 0 r interrupt flag for out endpoint 5 4 outep4if 0 r interrupt flag for out endpoint 4 3 outep3if 0 r interrupt flag for out endpoint 3 2 outep2if 0 r interrupt flag for out endpoint 2 1 outep1if 0 r interrupt flag for out endpoint 1 0 - 0 r0 unused 0xde06: usbcif ? common usb interrupt flags bit field name reset r/w description 7:4 - 0000 r0 unused 3 sofif 0 r start-of-frame interrupt flag 2 rstif 0 r reset interrupt flag 1 resumif 0 r resume interrupt flag 0 suspendif 0 r suspend interrupt flag 0xde07: usbiie ? in endpoints and ep0 interrupt enable mask bit field name reset r/w description 7:6 - 00 r0 unused 5 inep5ie 1 r/w in endpoint 5 interrupt enable 4 inep4ie 1 r/w in endpoint 4 interrupt enable 3 inep3ie 1 r/w in endpoint 3 interrupt enable 2 inep2ie 1 r/w in endpoint 2 interrupt enable 1 inep1ie 1 r/w in endpoint 1 interrupt enable 0 ep0ie 1 r/w endpoint 0 interrupt enable
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 178 of 252 0xde09: usboie ? out endpoints interrupt enable mask bit field name reset r/w description 7:6 - 00 r0 unused 5 outep5ie 1 r/w out endpoint 5 interrupt enable 4 outep4ie 1 r/w out endpoint 4 interrupt enable 3 outep3ie 1 r/w out endpoint 3 interrupt enable 2 outep2ie 1 r/w out endpoint 2 interrupt enable 1 outep1ie 1 r/w out endpoint 1 interrupt enable 0 - 0 r0 unused 0xde0b: usbcie ? common usb interrupt enable mask bit field name reset r/w description 7:4 - 0000 r0 unused 3 sofie 0 r/w start-of-frame interrupt enable 2 rstie 1 r/w reset interrupt enable 1 resumeie 1 r/w resume interrupt enable 0 suspendie 0 r/w suspend interrupt enable 0xde0c: usbfrml ? current frame number (low byte) bit field name reset r/w description 7:0 frame[7:0] 0x00 r low byte of 11-bit frame number 0xde0d: usbfrmh ? current frame number (high byte) bit field name reset r/w description 7:3 - 00000 r0 always 0 2:0 frame[10:8] 000 r high byte of 11-bit frame number 0xde0e: usbindex ? current endpoint index register bit field name reset r/w description 7:4 - 0000 r0 always 0 3:0 usbindex[3:0] 0000 r/w endpoint selected. must be set to value in the range 0 ? 5.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 179 of 252 0xde10: usbmaxi ? max. packet size for in endpoint bit field name reset r/w description 7:0 usbmaxi[7:0] 0x00 r/w maximum packet size in units of 8 bytes for in endpoint selected by usbindex register. the value of this register should correspond to the wmaxpacketsize field in the standard endpoint descriptor for the endpoint. this register must not be set to a value grater than the available fifo memory for the endpoint. 0xde11: usbcs0 ? ep0 control and status (usbindex = 0) bit field name reset r/w description 7 clr_setup_end 0 r/w h0 set this bit to clear the setup_end bit. it will be cleared automatically. 6 clr_outpkt_rdy 0 r/w h0 set this bit to clear the outpkt_rdy bit. it will be cleared automatically. 5 send_stall 0 r/w h0 set this bit to make the usb controller reply with a stall during the next transfer. this bit is automatically cleared. used to terminate the current transaction. 4 setup_end 0 r this bit is set if the control transfer ends due to a premature end of control transfer. the fifo will be flushed and the interrupt flag usbiif.ep0if will be set. set the clr_setup_end bit to clear this bit. 3 data_end 0 r/w h0 this bit is used to si gnal the end of a data transfer. this bit must be set in the following three situations: ? when the last data packet has been loaded and inpkt_rdy is set ? when the last data packet has been unloaded and clr_outpkt_rdy is set ? when inpkt_rdy is set without having loaded the fifo (for sending a zero length data packet). the usb controller will clear this bit automatically. 2 sent_stall 0 r/w h1 this bit is set when a stall has been sent. the interrupt flag usbiif.ep0 will be set. this bit must be cleared from firmware. 1 inpkt_rdy 0 r/w h0 set this bit when a data packet has been loaded into the ep0 fifo to notify the usb controller that a new data packet is ready to be transferred. when the data packet has been sent, this bit is cleared and the interrupt flag is set. 0 outpkt_rdy 0 r data packet received. this bit is set when an incoming data packet has been placed in the out fifo. set the clr_outpkt_rdy bit to clear this bit. the interrupt flag is also set when this bit is set.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 180 of 252 0xde11: usbcsil ? in ep{1-5} control and status low bit field name reset r/w description 7 - 0 r0 unused 6 clr_data_tog 0 r/w h0 setting this bit will reset the data toggle to 0. thus, setting this bit will force the next data packet to be a data0 packet. this bit is automatically cleared. 5 sent_stall 0 r/w this bit is set when a stall has been sent. the fifo will be flushed and the inpkt_rdy bit is set to 0. this bit must be cleared from firmware. 4 send_stall 0 r/w set this bit to make the usb controller reply with a stall handshake when receiving in tokens. firmware must clear this bit to end the stall condition. it is not possibl e to stall an isochronous endpoint, thus this bit will only have effect if the in endpoint is configured as bulk/interrupt. 3 flush_packet 0 r/w h0 flush next packet that is ready for transfer. the inpkt_rdy bit will be cleared. if there are two packets in the in fifo due to double buffering, this bit must be set twice to completely flush the in fifo. this bit is automatically cleared. 2 underrun 0 r/w this bit is set when inpkt_rdy has not been set when an in token is received. a zero length data packet is transmitted in response to the in token. this bit is only used for isochronous endpoints. firmware should clear this bit. 1 pkt_present 0 r this bit is set when there is at least one packet in the in fifo. 0 inpkt_rdy 0 r/w h0 set this bit when a data packet has been loaded into the in fifo to notify the usb controller that a new data packet is ready to be transferred. when the data packet has been sent, this bit is cleared and the interrupt flag is set. 0xde12: usbcsih ? in ep{1-5} control and status high bit field name reset r/w description 7 autoset 0 r/w when this bit is set, the inpkt_rdy bit is automatically set when a data packet of maximum size (specified by usbmaxi) has been loaded into the in fifo. 6 iso 0 r/w selects in endpoint type. 0 ? bulk/interrupt 1 ? isochronous 5:4 - 10 r unused 3 force_data_tog 0 r/w setting this bit will force the in endpoint data toggle to switch and the data packet to be flushed from the in fifo even though an ack was received. this feature can be useful when reporting rate feedback for isochronous endpoints. 2:1 - 0 r0 unused 0 in_dbl_buf 0 r/w set this bit to enable double buffering of data packets.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 181 of 252 0xde13: usbmaxo ? max. packet size for out endpoint bit field name reset r/w description 7:0 usbmaxo[7:0] 0x00 r/w maximum packet size in units of 8 bytes for out endpoint selected by usbindex register. the value of this register should correspond to the wmaxpacketsize field in the standard endpoint descriptor for the endpoint. this register must not be set to a value grater than the available fifo memory for the endpoint. 0xde14: usbcsol ? out ep{1-5} control and status low bit field name reset r/w description 7 clr_data_tog 0 r/w h0 setting this bit will reset the data toggle to 0. thus, setting this bit will force the next data packet to be a data0 packet. this bit is automatically cleared. 6 sent_stall 0 r/w this bit is s et when a stall has been sent. this bit must be cleared from firmware. 5 send_stall 0 r/w set this bit to make the usb controller reply with a stall handshake. firmware must clear this bit to end the stall condition. it is not possible to stall an isochronous endpoint, thus this bit will only have effect if the out endpoint is configured as bulk/interrupt. 4 flush_packet 0 r/w h0 flush next packet that is to be read from the out fifo. if there are two packets in the in fifo due to double buffering, this bit must be set twice to completely flush the in fifo. this bit is automatically cleared. 3 data_error 0 r this bit is set if there is a crc or bit-stuff error in the packet received. cleared when outpkt_rdy is cleared. this bit will only be valid if the out endpoint type is isochronous. bu lk/interrupt endpoints use retransmission when errors occur while there is no retransmission for is ochronous endpoints. 2 overrun 0 r/w this bit is set when an out packet cannot be loaded into the out fifo and the out endpoint type is isochronous. firmware should clear this bit. 1 fifo_full 0 r out fifo full. no more packets can be loaded. 0 outpkt_rdy 0 r/w this bit is set when a packet has been successfully received and is ready to be read from out fifo. this bit should be cleared as soon as the packet has been unloaded from the fifo. the interrupt flag for the out endpoint is set when this bit is set.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 182 of 252 0xde15: usbcsoh ? out ep{1-5} control and status high bit field name reset r/w description 7 autoclear 0 r/w when this bit is set, the outpkt_rdy bit is automatically cleared when a data packet of maximum size (specified by usbmaxo) has been unloaded into the out fifo. 6 iso 0 r/w selects out endpoint type. 0 ? bulk/interrupt 1 ? isochronous 5:4 - 00 r/w unused. must be 0. 3:1 - 000 r0 unused 0 out_dbl_buf 0 r/w set this bit to enable double buffering of data packets. 0xde16: usbcnt0 ? number of received bytes in ep0 fifo (usbindex = 0) bit field name reset r/w description 7:6 - 00 r0 unused. 5:0 usbcnt0[5:0] 0x00 r number of received bytes into ep 0 fifo. only valid when outpkt_rdy is set. 0xde16: usbcntl ? number of bytes in out fifo low bit field name reset r/w description 7:0 usbcnt[7:0] 0x00 r number of received bytes into out fifo selected by usbindex register. only valid when outpkt_rdy is set. 0xde17: usbcnth ? number of bytes in out fifo high bit field name reset r/w description 7:3 - 0x00 r0 unused 2:0 usbcnt[10:8] 0x00 r number of received bytes into out fifo selected by usbindex register. only valid when outpkt_rdy is set. 0xde20: usbf0 ? endpoint 0 fifo bit field name reset r/w description 7:0 usbf0[7:0] 0x00 r/w endpoint 0 fifo r egister. reading this register causes one byte to be extracted from the ep0 fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep0 fifo. note: the fifo memory for ep0 is used for both incoming and outgoing data packets.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 183 of 252 0xde22: usbf1 ? endpoint 1 fifo bit field name reset r/w description 7:0 usbf1[7:0] 0x00 r/w endpoint 1 fifo r egister. reading this register causes one byte to be extracted from the ep1 out fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep1 in fifo. 0xde24: usbf2 ? endpoint 2 fifo bit field name reset r/w description 7:0 usbf2[7:0] 0x00 r/w endpoint 2 fifo r egister. reading this register causes one byte to be extracted from the ep2 out fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep2 in fifo. 0xde26: usbf3 ? endpoint 3 fifo bit field name reset r/w description 7:0 usbf3[7:0] 0x00 r/w endpoint 3 fifo r egister. reading this register causes one byte to be extracted from the ep3 out fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep3 in fifo. 0xde28: usbf4 ? endpoint 4 fifo bit field name reset r/w description 7:0 usbf4[7:0] 0x00 r/w endpoint 4 fifo r egister. reading this register causes one byte to be extracted from the ep4 out fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep4 in fifo. 0xde2a: usbf5 ? endpoint 5 fifo bit field name reset r/w description 7:0 usbf5[7:0] 0x00 r/w endpoint 5 fifo r egister. reading this register causes one byte to be extracted from the ep5 out fifo. the value of the extracted value is returned. writing to this register inserts one byte with the value written into the ep5 in fifo.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 184 of 252 13.16 flash controller the CC2510FX/cc2511fx contains 8, 16 or 32 kb flash memory for storage of program code. the flash memory is programmable from the user software. the flash controller handles writing and erasing the embedded flash memory. the flash memory consists of 8, 16 or 32 pages of 1024 bytes each, depending on the total flash size. the flash memory is byte-addressable from the cpu and 16-bit word-programmable. the flash controller has the following features: ? 16-bit word programmable ? page erase ? lock bits for write-protection and code security ? flash erase timing 20 ms ? flash write timing 20 s 13.16.1 flash write data is written to the flash memory by using a program command initiated by writing the flash control register, fctl . flash write operations can program any number of locations in the flash memory at a time ? it is however important to make sure the pages to be written are erased first. a write operation is performed using one out of two methods; ? through dma transfer ? through cpu sfr access. the dma transfer method is the preferred way to write to the flash memory. a write operation is initiated by writing a 1 to fctl.write . the address to start writing at, is given by faddrh:faddrl . during each single write operation fctl.swbsy is set high. during a write operation the data written to the fwdata register is forwarded to the flash memory. the flash memory is 16-bit word- programmable, meaning data is written as 16-bit words. therefore the actual writing to flash memory takes place each time two bytes have been written to fwdata . the cpu will not be able to access the flash, e.g. to read program code, while a flash write operation is in progress. therefore the program code executing the flash write must be executed from ram, meaning that the program code must reside in the area 0xf000 to 0xff00 in xdata/code memory space. when a flash write operation is executed from ram, the cpu continues to execute code from the next instruction after the write to fwdata , which initiated the flash write operation. the fctl.swbsy bit must be 0 before accessing the flash after a flash write, otherwise an access violation occurs. this also means that fctl.swbsy must be 0 before program execution can continue at a location in flash memory. 13.16.1.1 dma flash write when using dma write operations, the data to be written into flash is stored in data/xdata memory. a dma channel is configured to read th e data to be written from memory and write this data to the flash write data register, fwdata with the dma trigger event fl enabled. thus the flash controller will trigger a dma transfer when the flash write data register, fwdata , is ready to receive new data. the dma channel should be configured to perform a block to fixed, single mode, byte size transfers. when the dma channel is armed, starting a flash write will trigger the first dma transfer. figure 39 shows an example how a dma channel is configured and how a dma transfer is initiated to write a block of data from a location in xdata to flash memory.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 185 of 252 setup dma channel: srcaddr= destaddrr=fwdata vlen=0 len= wordsize=byte tmode=single mode trig=fl srcinc=yes destinc=no irqmask=yes m8=0 priority=high arm dma channel start flash write setup flash address ; write a consecutive block of data from xdata to consecutive locations in ; flash memory using dma ; assumes 26 mhz system clock is used ; mov dptr,#dmacfg ;load data pointer with address for dma ;channel configuration and ;start writing dma configuration mov a,#src_hi ;source data high address movx @dptr,a ; inc dptr ; mov a,#src_lo ;source data low address movx @dptr,a ; inc dptr ; mov a,#0dfh ;destination high address = high(x_fwdata) movx @dptr,a ; inc dptr ; mov a,#0afh ;destination low address = low(x_fwdata) movx @dptr,a ; inc dptr ; mov a,#blk_len ;block length movx @dptr,a ; inc dptr ; mov a,#012h ;8 bits, single mode, use fl trigger movx @dptr,a ; inc dptr ; mov a,#042h ;increment source by 1, don?t increment movx @dptr,a ;destination, mask interrupt, high dma ;priority mov dma0cfgl,#dmacfg_lo ;setup start address for current dma mov dma0cfgh,#dmacfg_hi ;configuration mov dmaarm,#01h ;arm dma channel 0 mov faddrh,#00h ;setup flash address high mov faddrl,#01h ;setup flash address low mov fwt,#2ah ;setup flash timing mov fctl,#02h ;start flash page write => trigger dma . . figure 39: flash write using dma
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 186 of 252 13.16.1.2 cpu flash write the cpu can also write directly to the flash. the cpu writes data to the flash write data register, fwdata . the flash memory is written each time two bytes have been written to fwdata . the cpu can poll the fctl.swbsy status to determine when the flash is ready for two more bytes to be written to fwdata. . performing flash write from xdata the steps required to start a flash write operation from xdata are shown in figure 40 on page 186. disable interrupts busy=1? setup fctl, fwt, faddrh, faddrl write fwdata yes ; write 32-bit word from xdata ; assumes 26 mhz system clock is used ; clr ea ;mask interrupts c1: mov a,fctl ;wait until flash controller is ready jb acc.7,c1 mov faddrh,#00h ;setup flash address high mov faddrl,#01h ;setup flash address low mov fwt,#2ah ;setup flash timing mov fctl,#02h ;set flash page write mov fwdata,#12h ;first byte mov fwdata,#34h ;second byte, initiates write figure 40 : flash write performed from xdata 13.16.2 flash page erase a page erase is initiated by setting fctl.erase to 1. the page addressed by faddrh[6:1] is erased when a page erase is initiated. note that if a page erase is initiated simultaneously with a page write, i.e. fctl.write is set to 1, the page erase will be performed before the page write operation. the fctl.busy bit can be polled to see when the page erase has completed. note: if flash erase operations are performed from within flash memory and the watchdog timer is enabled, a watchdog timer interval must be selected that is longer than 20 ms, the duration of the flash erase operation, so that the cpu will manage to clear the watchdog timer. performing flash erase from flash memory.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 187 of 252 the steps required to perform a flash page erase from within flash memory are outlined in figure 41. note that, while executing program code from within flash memory, when a flash erase or write operation is initiated, program execution w ill resume from the next instruction when the flash controller has completed the operation. ; erase page in flash memory ; assumes 26 mhz system clock is used ; clr ea ;mask interrupts c1: mov a,fctl ;wait until flash controller is ready jb acc.7,c1 mov faddrh,#00h ;setup flash address high mov faddrl,#01h ;setup flash address low mov fwt,#2ah ;setup flash timing mov fctl,#01h ;erase page ret ;continues here when flash is ready figure 41: flash page erase performed from flash memory 13.16.3 flash lock protection for software protection purposes a set of lock protection bits can be written once after each chip erase has been performed. the lock protect bits can only be written through the debug interface. there are three kinds of lock protect bits as described in this section. the flash lock bits reside at location 0x000 in the flash information page as described in section 12.11. the lsize[2:0] lock protect bits are used to define a section of the flash memory which is write protected. the size of the write protected area can be set by the lsize[2:0] lock protect bits in sizes of eight steps from 0 to 32 kb. notice that the only supported value for lsize[2:0] is 0 and 7 for cc2510f8, cc2511f8, cc2510f16 and cc2511f16. the second type of lock protect bits is bblock , which is used to lock the boot sector page (page 0 ranging from address 0 to 0x03ff). when bblock is set to 0, the boot sector page is locked. the third type of lock protect bit is dbglock , which is used to disable hardware debug support through the debug interface. when dbglock is set to 0, all debug commands are disabled. the lock protect bits are written as a normal flash write to fwdata , but the debug interface needs to select the flash information page first instead of the flash main page which is the default setting. the information page is selected through the debug configuration which is written through the debug interface only. refer to section 12.9 on page 60 for details on how to select the flash information page using the debug interface. table 54 defines the byte containing the flash lock protection bits. note that this is not an sfr register, but instead the byte stored at location 0x000 in flash information page.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 188 of 252 table 54: flash lock protection bits definition bit name description 7:5 - reserved, write as 0 boot block lock 0 page 0 is write protected 4 bblock 1 page 0 is writeable, unless lsize is 000 lock size. sets the size of the upper flash area which is write protected. byte sizes are listed below 000 32k bytes (all pages) 001 24k bytes (cc2510f32 and cc2511f32 only) 010 16k bytes (cc2510f32 and cc2511f32 only) 011 8k bytes (cc2510f32 and cc2511f32 only) 100 4k bytes (cc2510f32 and cc2511f32 only) 101 2k bytes (cc2510f32 and cc2511f32 only) 110 1k bytes (cc2510f32 and cc2511f32 only) 3:1 lsize[2:0] 111 0 bytes (no pages) debug lock bit 0 disable debug commands 0 dbglock 1 enable debug commands 13.16.4 flash write timing the flash controller contains a timing generator which controls the timing sequence of flash write and erase operations. the timing generator uses the information set in the flash write timing register, fwt.fwt[5:0] , to set the internal timing. fwt.fwt[5:0] must be set to a value according to the currently selected system clock frequency. the value set in the fwt.fwt[5:0] shall be set according to the system clock frequency by the following equation. 9 10 * 16 21000 f fwt ? = where f is the system clock frequency. the initial value held in fwt.fwt[5:0] after a reset is 0x11 which corresponds to 13 mhz cpu clock frequency (high speed rc oscillator). the fwt values for the possible system clock frequencies are given in table 55. system clock frequency (mhz) fwt 13 0x11 16 0x15 24 0x20 26 0x23 table 55: flash timing (fwt) values 13.16.5 flash controller registers the flash controller registers are described in this section.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 189 of 252 fctl (0xae) ? flash control bit name reset r/w description 7 busy 0 r indicates that write or erase is in operation 6 swbsy 0 r indicates that single write is busy; avoid writing to fwdata register while this is true 5 - 0 r/w not used. 4 contrd r/w 0 continuous read enable mode 0 avoid wasting power; turn on read enables to flash only when needed 1 enable continuous read enables to flash when read is to be done. reduces internal switching of read enables, but greatly increases power consumption. 3:2 0 r/w not used. 1 write 0 r0/w page write. start writing page given by faddrh:faddrl . if erase is set to 1, a page erase is performed before the write. 0 erase 0 r0/w page erase. erase page that is given by faddrh:faddrl fwdata (0xaf) ? flash write data bit name reset r/w description 7:0 fwdata[7:0] 0x00 r/w flash write data. data written to fwdata is written to flash when fctl.write is set to 1. faddrh (0xad) ? flash address high byte bit name reset r/w description 7:6 - 00 r/w not used 5:0 faddrh[6:0] 0x00 r/w high byte of flash address bits 5:1 will select page to access, while bit 0 is msb of row access. faddrl (0xac) ? flash address low byte bit name reset r/w description 7:0 faddrl[7:0] 0x00 r/w low byte of flash address bit 0 of faddrh and bits 7:6 will select which row to write to, while bits 5:0 will select which location to write to. fwt (0xab) ? flash write timing bit name reset r/w description 7:6 - 00 r/w not used 5:0 fwt[5:0] 0x25 r/w flash write timing. c ontrols flash timing generator.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 190 of 252 14 crystal oscillator 14.1 CC2510FX crystal oscillator a crystal in the frequency range 26 mhz- 27 mhz must be connected between the xosc_q1 and xosc_q2 pins. the oscillator is designed for parallel mode operation of the crystal. in addition, loading capacitors (c201 and c211) for the crystal are required. the loading capacitor values depend on the total load capacitance, c l , specified for the crystal. the total load capacitance seen between the crystal terminals should equal c l for the crystal to oscillate at the specified frequency. parasitic l c c c c + + = 201 211 1 1 1 the parasitic capacitance is constituted by pin input capacitance and pcb stray capacitance. total parasitic capacitance is typically 2.5 pf. the crystal oscillator circuit is shown in figure 7. typical component values for different values of c l are given in table 9. the crystal oscillator is amplitude regulated. this means that a high current is used to start up the oscillations. when the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 vpp signal swing. this ensures a fast start-up, and keeps the drive level to a minimum. the esr of the crystal should be within the specification in order to ensure a reliable start-up (see section table 9 on page 15). 14.2 cc2511fx crystal oscillator the cc2511fx requires a 48 mhz frequency crystal to be used. if a fundamental crystal is used, only the loading capacitor values need to be changed compared to the CC2510FX crystal oscillator. if a 3 rd overtone crystal is used, an additional inductor and capacitor is needed. figure 9 shows this configuration. values for capacitors and the inductor are given in table 27.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 191 of 252 15 radio pa lna 0 90 freq synth adc adc demodulator fec / interleaver packet handler modulator cpu interface radio control rf_p rf_n figure 42: CC2510FX/cc2511fx radio module a simplified block diagram of the radio module in the CC2510FX/cc2511fx is shown in figure 42. CC2510FX/cc2511fx features a low-if receiver. the received rf signal is amplified by the low-noise amplifier (lna) and down-converted in quadrature (i and q) to the intermediate frequency (if). at if, the i/q signals are digitized by the adcs. automatic gain control (agc), fine channel filtering, demodulation bit/packet synchronization is performed digitally. the transmitter part of CC2510FX/cc2511fx is based on direct synthesis of the rf frequency. the frequency synthesizer includes a completely on-chip lc vco and a 90 degrees phase shifter for generating the i and q lo signals to the down-conversion mixers in receive mode. the 26/48 mhz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the adc and the digital part. an sfr register interface is used for data buffer access from the cpu. configuration and status registers are accessed through registers mapped to xdata memory. the digital baseband includes support for channel configuration, packet handling and data buffering. an on-chip voltage regulator delivers a regulated 1.8 v supply voltage. 15.1 command strobes the cpu uses a set of command strobes to control operation of the radio in CC2510FX/cc2511fx . command strobes may be viewed as single byte instructions which each control some function of the radio. these command strobes must be used to enable
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 192 of 252 the frequency synthesizer, enable receive mode, enable transmit mode and other functions. the command strobes are issued by writing to the rfst sfr register. the list of all strobe commands which are defined is given in table 56. transmit mode receive mode idle manual freq. synth. calibration frequency synthesizer on sfstxon srx stx stx stx or rxoff_mode=10 rxoff_mode=00 srx or txoff_mode=11 sidle scal txoff_mode=00 sfstxon or rxoff_mode=01 srx or stx or sfstxon txoff_mode=01 frequency synthesizer startup, optional calibration, settling optional freq. synth. calibration default state when the radio is not receiving or transmitting. typ. current consumption in radio: 1.8ma. used for calibrating frequency synthesizer upfront (entering receive or transmit mode can then be done quicker). transitional state. typ. current consumption in radio: 7.6ma. frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. transitional state. typ. current consumption in radio: 7.6ma. frequency synthesizer is on, ready to start transmitting. transmission starts very quickly after receiving the stx command strobe.typ. current consumption in radio: 7.6ma. typ. current consumption in radio: 11.5ma at -12dbm output, 15.4ma at -6dbm output, 21.6ma at 0dbm output. typ. current consumption: from 13.3ma (strong input signal) to 15.6ma (weak input sgnal). optional transitional state. typ. current consumption: 7.6ma. idle figure 43: simplified state diagram, with typical usage and current consumption in radio
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 193 of 252 rfst value command strobe name description 0x00 sfstxon enable and calibrate frequency synthesizer (if mcsm0.fs_autocal =1). while in rx / tx issuing this command strobe will force the radio to go to a wait state where only the synthesizer is running (for quick rx / tx turnaround). 0x01 scal calibrate frequency synthesizer and turn it off (enables quick start). 0x02 srx enable rx. perform calibration first if coming from idle and mcsm0.fs_autocal =1. 0x03 stx in idle state: enable tx. perform calibration first if mcsm0.fs_autocal =1. if in rx state and cca is enabled: only go to tx if channel is clear. 0x04 sidle exit rx / tx, turn off frequency synthesizer. 0x05 safc perform afc adjustment of the frequency synthesizer all others snop no operation. table 56: command strobes 15.2 radio registers the operation of the radio is configured through a set of rf registers. these rf registers are mapped to xdata memory space as shown in figure 10 on page 36. in addition to configuration registers, the rf registers also provide status information from the radio. the rf registers cont rol/status bits are referred to where appropriate in the following sections while section 15.18 on page 216 gives a full description of all rf registers. 15.3 interrupts the radio is associated with two interrupt vectors on the cpu. these are the rftxrx interrupt (interrupt 0) and the rfif interrupt (interrupt 12) with the following functions ? rftxrx: rx data ready or tx data complete ? rf: all other rfif interrupt flags the rf interrupt vector combines the interrupts in rfif shown on page 194. note that these rf interrupts are rising- edge triggered. thus an interrupt is generated when e.g. t he sfd status flag goes from 0 to 1. the rf interrupt can also be used to trigger a timer capture in timer 1. the rf interrupt flags are described in the next section. 15.3.1 interrupt registers two of the main interrupt control sfr registers are used to enable the rf and rftxrx interrupts. these are the following: ? rftxrx : ien0. rftxrxie ? rf : ien2.rfie two main interrupt flag sfr registers hold the rf and rferr interrupt flags. these are the following: ? rftxrx : tcon. rftxrx ? rf : s1con.rfif refer to section 12.7 for details about the interrupts. the rf interrupt is the combined interrupt from six different sources in the radio. two sfr registers are used for setting the six individual rfif radio interrupt flags and interrupt enables. these are the rfif and rfim registers. the interrupt flags in sfr register rfif show the status for each interrupt source for the rf interrupt vector. the interrupt enable bits in rfim are used to disable individual interrupt sources for the rf interrupt vector. note that masking
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 194 of 252 an interrupt source in rfim does not affect the update of the status in the rfif register. due to the use of the individual interrupt masks in rfim , and the main interrupt mask for the rf interrupt given by ien2.rfie there is two-layered masking of this interrupt. special attention needs to be taken when processing this type of interrupt as described below. to clear the rf interrupt, s1con.rfif and the interrupt flag in rfif need to be cleared. the order and method of doing this is shown in figure 44. note that s1con is cleared after rfif , otherwise s1con.rfif could be set once again due to the same interrupt. mov rfif,#00h ;clear all interrupt flags mov s1con,#00h ;clear main interrupt flags mov rfim,rfim ;set interrupt mask figure 44: clearing rf interrupt rfif (0xe9) ? rf interrupt flags bit name reset r/w description tx underflow. 0 no interrupt pending 7 irq_txunf 0 r/w0 1 interrupt pending rx overflow. 0 no interrupt pending 6 irq_rxovf 0 r/w0 1 interrupt pending rx timeout, no packet has been received in the programmed period. 0 no interrupt pending 5 irq_timeout 0 r/w0 1 interrupt pending packet received/transmitted. also us ed to detect underflow/overflow conditions. 0 no interrupt pending 4 irq_done 0 r/w0 1 interrupt pending carrier sense. 0 no interrupt pending 3 irq_cs 0 r/w0 1 interrupt pending preamble quality reached. 0 no interrupt pending 2 irq_pqt 0 r/w0 1 interrupt pending clear channel assessment 0 no interrupt pending 1 irq_cca 0 r/w0 1 interrupt pending start of frame delimiter, sync word detected 0 no interrupt pending 0 irq_sfd 0 r/w0 1 interrupt pending
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 195 of 252 rfim (0x91) ? rf interrupt mask bit name reset r/w description tx underflow. 0 interrupt disabled 7 im_txunf 0 r/w 1 interrupt enabled rx overflow. 0 interrupt disabled 6 im_rxovf 0 r/w 1 interrupt enabled rx timeout, no packet has been received in the programmed period. 0 interrupt disabled 5 im_timeout 0 r/w 1 interrupt enabled packet received/transmitted. also us ed to detect underflow/overflow conditions. 0 interrupt disabled 4 im_done 0 r/w 1 interrupt enabled carrier sense. 0 interrupt disabled 3 im_cs 0 r/w 1 interrupt enabled preamble quality reached. 0 interrupt disabled 2 im_pqt 0 r/w 1 interrupt enabled clear channel assessment 0 interrupt disabled 1 im_cca 0 r/w 1 interrupt enabled start of frame delimiter, sync word detected 0 interrupt disabled 0 im_sfd 0 r/w 1 interrupt enabled 15.4 tx/rx data transfer transmit data is written to the radio when writing to the rf data register, rfd . received data is returned when the rfd register is read. it is required that the user software uses fifo structures in memory to implement rx and tx fifos. in most cases it is recommended that the transfer of data between fifos in memory and the rf data register, rfd , involves the use of dma channels with rfd as source/destination and dma trigger radio. for description on the usage of dma, refer to section 13.2 on page 84. a simple example of writing tx data to the radio is shown in figure 45. this example does not use dma, but illustrates some of the basic principles.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 196 of 252 ; start radio tx ; simple example, assumes required frequency, modulation format and ; data rate has been set in rf registers ; mov dptr,pa_table0 ;setting pa output power mov a,#0ffh ; movx @dptr,a ; mov clkcon,#00h ;select 26 mhz xosc mov rfst,#03h ;start tx with stx command strobe c1: jnb ie0,c1 ;wait for interrupt flag telling radio is clr ie0 ;ready to accept data, then write mov rfd,#02h ;first data to radio, packet length=2 c2: jnb ie0,c2 ;wait for radio clr ie0 ; mov rfd,#12h ;send first byte in payload c3: jnb ie0,c3 ;wait for radio clr ie0 ; mov rfd,#34h ;send second byte in payload ;done figure 45: simple rf transmit example 15.5 data rate programming the data rate used when transmitting, or the data rate expected in receive is programmed by the mdmcfg3.drate_m and the mdmcfg4.drate_e configuration registers. the data rate is given by the formula below. as the formula shows, the programmed data rate depends on the crystal frequency. () xosc e drate data f m drate r ? ? + = 28 _ 2 2 _ 256 the following approach can be used to find suitable values for a given data rate: 256 2 2 _ 2 log _ _ 28 20 2 ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = e drate xosc data xosc data f r m drate f r e drate if drate_m is rounded to the nearest integer and becomes 256, increment drate_e and use drate_m =0. the data rate can be set from 1.2 kbps to 500 kbps with the minimum step size as shown in table 57. data rate start typical data rate data rate stop data rate step size 0.8 kbps 1.2 / 2.4 kbps 3.17 kbps 0.0062 kbps 3.17 kbps 4.8 kbps 6.35 kbps 0.0124 kbps 6.35 kbps 9.6 kbps 12.7 kbps 0.0248 kbps 12.7 kbps 19.6 kbps 25.4 kbps 0.0496 kbps 25.4 kbps 38.4 kbps 50.8 kbps 0.0992 kbps 50.8 kbps 76.8 kbps 101.6 kbps 0.1984 kbps 101.6 kbps 153.6 kbps 203.1 kbps 0.3967 kbps 203.1 kbps 250 kbps 406.3 kbps 0.7935 kbps 406.3 kbps 500 kbps 500 kbps 1.5869 kbps table 57: data rate step size
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 197 of 252 15.6 receiver channel filter bandwidth in order to meet different channel width requirements, the receiver channel filter is programmable. the mdmcfg4.chanbw_e and mdmcfg4.chanbw_m configuration registers control the re ceiver channel filter bandwidth, which scales with the crystal oscillator frequency. the following formula gives the relation between the register settings and the channel filter bandwidth: e chanbw xosc channel m chanbw f bw _ 2 ) _ 4 ( 8 + ? = the CC2510FX/cc2511fx supports channel filter bandwidths shown in table 58. table 58: channel filter bandwidths [khz] (26 mhz crystal) for best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupi es at most 80% of the channel filter bandwidth. the channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. the following example illustrates this: with the channel filter bandwidth set to 600 khz, the signal should stay within 80% of 600 khz, which is 480 khz. assuming 2.44 ghz frequency and 20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is 40 ppm of 2.44 ghz, which is 98 khz. if the whole transmitted signal bandwidth is to be received within 480 khz, the transmitted signal bandwidth should be maximum 480 khz?298 khz, which is 284 khz. 15.7 demodulator, symbol synchronizer and data decision CC2510FX/cc2511fx contains an advanced and highly configurable demodulator. channel filtering and frequency offset compensation is performed digitally. to generate the rssi level (see section 15.10.3 for more information) the signal level in the channel is estimated. data filtering is also included for enhanced performance. 15.7.1 frequency offset compensation when using fsk or msk modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. this value is available in the freqest status register. by issuing the safc command strobe, the measured offset, freqest.freqoff_est, can automatically be used to adjust the frequency offset programming in the frequency synthesizer. this will add the current rx frequency offset estimate to the value in fsctrl0.freqoff , which adjust the synthesizer frequency. thus, the frequency offset will be compensated in both rx and tx when the safc command strobe is used. mdmcfg4. mdmcfg4.chanbw_e chanbw_m 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 198 of 252 to avoid compensating for frequency offsets measured without a valid signal in the rf channel, freqest.freqoff_est is copied to an internal register when issuing the safc strobe in rx, and when a sync word is detected. if safc was issued in rx, this internal value is added to fsctrl0.freqoff after exiting rx. issuing safc when not in rx will immediately add the internal register value to fsctrl0.freqoff . thus, the safc strobe should be issued when currently receiving a packet, or outside the rx state. note that frequency o ffset compensation is not supported for ook modulation. 15.7.2 bit synchronization the bit synchronization algorithm extracts the clock from the incoming symbols. the algorithm requires that the expected data rate is programmed as described in section 15.5 on page 196. re- synchronization is pe rformed continuously to adjust for error in the incoming symbol rate. 15.7.3 byte synchronization byte synchronization is achieved by a continuous sync word search. the sync word is a 16 or 32 bit configurable field that is automatically inserted at the start of the packet by the modulator in transmit mode. the demodulator uses this field to find the byte boundaries in the stream of bits. the sync word w ill also function as a system identifier, since only packets with the correct predefined sync word will be received. the sync word detector correlates against the user-configured 16- bit sync word. the correlation threshold can be set to 15/16 bits match or 16/16 bits match. the sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. the sync word is programmed with sync1 and sync0. in order to make false detections of sync words less likely, a mechanism called preamble quality indication (pqi) can be used to qualify the sync word. a threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. see section 15.10.2 on page 203 for more details. 15.8 packet handling hardware support the CC2510FX/cc2511fx has built-in hardware support for packet oriented radio protocols. in transmit mode, the packet handler will add the following elements to the packet stored to be transmitted: ? a programmable number of preamble bytes. four preamble bytes are recommended. ? a two byte synchronization word. can be duplicated to give a 4-byte sync word. (recommended). ? optionally whiten the data with a pn9 sequence. ? optionally interleave and forward error code the data. ? optionally compute and add a crc checksum over the data field. in receive mode, the packet handling support will de-constru ct the data packet: ? preamble detection. ? sync word detection. ? optional one byte address check. ? optionally compute and check crc. ? optionally append two status bytes (see table 59 and table 60) with rssi value, link quality indication and crc status. bit field name description 7:0 rssi rssi value table 59: received packet status byte 1 (first byte appended after the data)
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 199 of 252 bit field name description 7 crc_ok 1: crc for received data ok (or crc disabled) 0: crc error in received data 6:0 lqi the link quality indicator estimates how easily a received signal can be demodulated table 60: received packet status byte 2 (second byte appended after the data) note that register fields that control the packet handling features should only be altered when CC2510FX/cc2511fx is in the idle state. 15.8.1 data whitening from a radio perspective, the ideal over the air data are random and dc free. this results in the smoothest power distribution over the occupied bandwidth. this also gives the control loops in the receiver uniform operation conditions (no data dependencies). real world data often contain long sequences of zeros and ones. performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver. with CC2510FX/cc2511fx , this can be done automatically by setting pktctrl0.white_data=1 . all data, except the preamble and the sync word, are then xor-ed with a 9-bit pseudo- random (pn9) sequence before being transmitted. at the receiver end, the data are xor-ed with the same pseudo-random sequence. this way, the whitening is reversed, and the original data appear in the receiver. setting pktctrl0.white_data=1 is recommended for all uses, except when over-the-air compatibility with other systems is needed. 15.8.2 packet format the format of the data packet can be configured and consists of the following items: ? preamble ? synchronization word ? length byte or constant programmable packet length ? optional address byte ? payload ? optional 2 byte crc preamble bits (1010...1010) sync word length field address field data field crc-16 optional crc-16 calculation optionally fec encoded/decoded 8 x n bits 16/32 bits 8 bits 8 bits 8 x n bits 16 bits optional data whitening legend: inserted automatically in tx, processed and removed in rx. optional user-provided fields processed in tx, processed but not removed in rx. unprocessed user data (apart from fec and/or whitening) figure 46: packet format
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 200 of 252 the preamble pattern is an alternating sequence of ones and zeros (01010101?). the minimum length of the preamble is programmable. when enabling tx, the modulator will start transmitting the preamble. when the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the rfd register. the number of preamble bytes is programmed with the mdmcfg1.num_preamble value. the synchronization word is a two-byte value set in the sync1 and sync0 registers. the sync word provides byte synchronization of the incoming packet. a one-byte sync word can be emulated by setting the sync1 value to the preamble pattern. it is also possible to emulate a 32 bit sync word by using mdmcfg2.sync_mode= 3 or 7. the sync word will then be repeated twice. CC2510FX/cc2511fx supports both fixed packet length protocols and variable length protocols. the maximum packet length is 255 bytes. for longer packets, infinite packet length mode must be used. fixed packet length mode is selected by setting pktctrl0.length_config=0. the desired packet length is set by the pktlen register. in variable packet length mode, pktctrl0.length_config=1, the packet length is configured by the first byte after the sync word. the packet length is defined as the payload data, excluding the length byte and the optional automatic crc. the pktlen register is used to set the maximum packet length allowed in rx. any packet received with a length byte with a value greater than pktlen will be discarded. with pktctrl0.length_config =2, the packet length is set to infinite and transmission and reception will continue until turned off manually. the infinite mode can be turned off while a packet is being transmitted or received. as described in the next section, this can be used to support packet formats with different length configuration than natively supported by CC2510FX/cc2511fx .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 201 of 252 15.8.2.1 arbitrary length field configuration the fixed length field can be reprogrammed during receive and transmit. this opens th e possibility to have a different length field configuration than supported for variable length packets. at the start of reception, the packet length is set to a large value. the cpu reads out enough bytes to interpret the length field in the packet. then the pktlen value is set according to this value. the end of packet will occur when the byte counter in the packet handler is equal to the pktlen register. thus, the cpu must be able to program the correct length, before the internal counter reaches the packet length. by utilizing the infinite packet length option, arbitrary packet length is available. at the start of the packet, the infinite mode must be active. on the tx side, the pktlen register is set to mod(length, 256). on the rx side the mcu reads out enough bytes to interpret the length field in the packet and sets the pktlen register to mod(length, 256). when less than 256 bytes remains of the packet the mcu disables infinite packet length and activates fixed length packets. when the internal byte counter reaches the pktlen value, the transmission or reception ends. automatic crc appending/checking can be used (by setting pktctrl0.crc_en to 1) when for example a 600-byte packet is to be transmitted, the mcu should do the following (see also figure 47): ? set pktctrl0.length_config =2 (10). ? pre-program the pktlen register to mod(600,256)=88. ? transmit at least 345 bytes. ? set pktctrl0.length_config =0 (00). ? the transmission ends when the packet counter reaches 88. a total of 600 bytes are transmitted. 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,......... .............. internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again length field transmitted and received. rx and tx pktlen value set to mod(600,256) = 88 infinite packet length enabled fixed packet length enabled when less than 256 bytes remains of packet 600 bytes transmitted and received figure 47: arbitary length field configuration
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 202 of 252 15.8.3 packet filtering in receive mode CC2510FX/cc2511fx supports two different packet-filtering criteria: address filtering and maximum length filtering. 15.8.3.1 address filtering setting pktctrl1.adr_chk to any other value than zero enables the packet address filter. the packet handl er engine will compare the destination address byte in the packet with the programmed node address in the addr register and the 0x00 broadcast address when pktctrl1.adr_chk=10 or both 0x00 and 0xff broadcast addresses when pktctrl1.adr_chk=11. if the received address matches a valid address, the packet is accepted and a rftxrx interrupt and a dma trigger is generated. if the address match fails, the packet is discarded and receive mode restarted (regardless of the mcsm1.rxoff_mode setting). if the received address matches a valid address when the packet length is set to infinite and address filtering is enabled, the first byte read from the radio will be 0xff, followed by the address byte and then the payload data. 15.8.3.2 maximum length filtering in the variable packet length mode the pktlen.packet_length register value is used to set the maximum allowed packet length. if the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the mcsm1.rxoff_mode setting). 15.8.4 packet handling in transmit mode the payload that is to be transmitted must be written into rfd . the first byte written must be the length byte when variable packet length is enabled. the length byte has a value equal to the payload of the packet (including the optional address byte). if fixed packet length is enabled, then the first byte written to rfd is interpreted as the destination address, if this feature is enabled in the device that receives the packet. the modulator will first send the programmed number of preamble bytes. if data is written to rfd , the modulator will send the two-byte (optionally 4-byte) sync word and then the payload written to rfd . if crc is enabled, the checksum is calculated over all the data pulled from rfd and the result is sent as two extra bytes at the end of the payload data. if whitening is enabled, the length byte, payload data and the two crc bytes will be whitened. this is done before the optional fec/interleaver stage. whitening is enabled by setting pktctrl0.white_data=1 . if fec/interleaving is enabled, the length byte, payload data and the two crc bytes will be scrambled by the interleaver, and fec encoded before being modulated. 15.8.5 packet handling in receive mode in receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. when found, the demodulator has obtained both bit and byte synchronism and will receive the first payload byte. if fec/interleaving is enabled, the fec decoder will start to de code the first payload byte. the interleaver will de-scramble the bits before any other processing is done to the data. if whitening is enabled, the data will be de- whitened at this stage. when variable packet length is enabled, the first byte is the length byte. the packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. if fixed packet length is used, the packet handler will accept the programmed number of bytes. next, the packet handler optionally checks the address and only continues the reception if the address matches. if automatic crc check is enabled, the packet handler computes crc and matches it with the appended crc checksum. at the end of the payload, the packet handler will optionally write tw o extra packet status bytes that contain crc status, link quality indication and rssi value. 15.9 modulation formats CC2510FX/cc2511fx supports amplitude, frequency and phase shift modulation formats. the desired modulation format is set in the mdmcfg2.mod_format register. optionally, the data stream can be manchester coded by the modulator and decoded by the demodulator. this option is enabled by setting mdmcfg2.manchester_en =1. manchester
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 203 of 252 encoding is not supported at the same time as using the fec/interleaver option. 15.9.1 frequency shift keying 2-fsk can optionally be shaped by a gaussian filter with bt=1, producing a gfsk modulated signal. the frequency deviation is programmed with the deviation_m and deviation_e values in the deviatn register. the value has an exponent/mantissa form, and the resultant deviation is given by: e deviation xosc dev m deviation f f _ 17 2 ) _ 8 ( 2 ? + ? = the symbol encoding is shown in table 61. format symbol coding 2fsk/gfsk ?0? ? deviation ?1? + deviation table 61: symbol encoding for fsk modulation 15.9.2 minimum shift keying when using msk 6 , the complete transmission (preamble, sync word and payload) will be msk modulated. phase shifts are performed with a constant transition time. the fraction of a symbol period used to change the phase can be modified with the deviatn.deviation_m setting. this is equivalent to changing the shaping of the symbol. the msk modulation format implemented in CC2510FX/cc2511fx inverts the sync word and data compared to e.g. signal generators. 6 identical to offset qpsk with half-sine shaping (data coding may differ) 15.9.3 amplitude modulation the supported amplitude modulation on-off keying (ook) simply turns on or off the pa to modulate 1 and 0 respectively. 15.10 received signal qualifiers and link quality information CC2510FX/cc2511fx has several qualifiers that can be used to increase the likelihood that a valid sync word is detected. 15.10.1 sync word qualifier if sync word detection in rx is enabled in register mdmcfg2 the CC2510FX/cc2511fx will not start writing received data to the rfd register and perform the packet filtering described in section 15.8.3 before a valid sync word has been detected. the sync word qualifier mode is set by mdmcfg2.sync_mode and is summarized in table 62. carrier sense in table 62 is described in section 15.10.4 mdmcfg2. sync_mode sync word qualifier mode 000 no preamble/sync 001 15/16 sync word bits detected 010 16/16 sync word bits detected 011 30/32 sync word bits detected 100 no preamble/sync, carrier sense above threshold 101 15/16 + carrier sense above threshold 110 16/16 + carrier sense above threshold 111 30/32 + carrier sense above threshold table 62: sync word qualifier mode 15.10.2 preamble quality threshold (pqt) the preamble quality threshold (pqt) sync- word qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above the programmed threshold. another use of the preamble quality threshold is as a qualifier for the optional rx termination timer. see section 15.12.3 on page 210 for details. the preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 4 each time a bit is received that is the same as the last bit. the counter saturates at 0 and 31. the threshold is configured with the register field pktctrl1.pqt . a threshold of 4 pqt for this counter is used to gate sync word detection.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 204 of 252 by setting the value to zero, the preamble quality qualifier of the sync word is disabled. a ?preamble quality reached? flag can also be observed in the status register bit pktstatus.pqt_reached . this flag asserts when the received signal exceeds the pqt. 15.10.3 rssi the rssi value is an estimate of the signal level in the chosen channel. this value is based on the current gain setting in the rx chain and the measured signal level in the channel. in rx mode, the rssi value can be read continuously from the r ssi status register. the rssi value is in db with ?db resolution. the rssi update rate depends on the receiver filter bandwidth (bw channel defined in section error! reference source not found. ) and agcctrl0.filter_length . length filter channel rssi bw f _ 2 8 2 ? ? = if pktctrl1.append_status is enabled the last rssi value of the packet is automatically added to the first byte appended after the data. the rssi value read from the rssi status register is a 2?s complement number. the following procedure can be used to convert the rssi reading to an absolute power level (rssi_dbm). 1) read the rssi status register 2) convert the reading from a hexadecimal number to a decimal number (rssi_dec) 3) if rssi_dec 128 then rssi_dbm = (rssi_dec - 256)/2 ? rssi_offset 4) else if rssi_dec < 128 then rssi_dbm = (rssi_dec)/2 ? rssi_offset error! reference source not found. table 63 gives typical values for the rssi_offset. figure 48 shows typical plots of rssi reading as a function of input power level for different data rates. data rate rssi_offset (decimal) 2.4 kbps 71 10 kbps 69 250 kbps 72 500 kbps 72 table 63: typical rssi_offset values
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 205 of 252 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 input power [dbm] rssi readout [dbm] 2.4 kbps 10 kbps 250 kbps 250 kbps, reduced current 500 kbps figure 48: typical rssi value vs. input power level for some typical data rates 15.10.4 carrier sense (cs) the carrier sense flag is used as a sync word qualifier and for cca. the cs flag can be set based on two conditions, which can be individually adjusted: ? cs is asserted when the rssi is above a programmable absolute threshold, and de-asserted when rssi is below the same threshold (with hysteresis). ? cs is asserted when the rssi has increased with a programmable number of db from one rssi sample to the next, and de-asserted when rssi has decreased with the same number of db. this setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with time varying noise floor. carrier sense (cs) can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. the signal can also be observed in the status register bit pktstatus.cs . other uses of carrier sense include the tx-if-cca function (see section 15.10.7 on page 206) and the optional fast rx termination (see section see section 15.12.3 on page 210 for details.). cs can be used to avoid interference from e.g. wlan. 15.10.5 cs absolute threshold the absolute threshold related to the rssi value is given by: max rssi gain thr abs sense carrier target magn thr ? + = _ _ _ _ the maximum possible gain can be reduced using the agcctrl2.max_lna_gain and agcctrl2.max_dvga_gain register fields. carrier_sense_abs_thr is programmable in 1 db steps from -7 db to + 7db. table 64 and table 65 show the rssi readout values at the cs threshold at 2.4 kbps and 250 kbps data rate respectively. the default carrier_sense_abs_thr = 0 (0 db) and magn_target = 3 (33 db) have been used.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 206 of 252 max_dvga_gain[1:0] 00 01 10 11 000 -99 -93 -87 -81.5 001 -97 -90.5 -85 -78.5 010 -93.5 -87 -82 -76 011 -91.5 -86 -80 -74 100 -90.5 -84 -78 -72.5 101 -88 -82.5 -76 -70 110 -84.5 -78.5 -73 -67 max_lna_gain[2:0] 111 -82.5 -76 -70 -64 table 64: typical rssi value in dbm at cs threshold with default magn_target at 2.4 kbps max_dvga_gain[1:0] 00 01 10 11 000 -96 -90 -84 -78.5 001 -94.5 -89 -83 -77.5 010 -92.5 -87 -81 -75 011 -91 -85 -78.5 -73 100 -87.5 -82 -76 -70 101 -85 -79.5 -73.5 -67.5 110 -83 -76.5 -70.5 -65 max_lna_gain[2:0] 111 -78 -72 -66 -60 table 65: typical rssi value in dbm at cs threshold with default magn_target at 250 kbps if the threshold is to be set high, e.g. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the max_lna_gain value and then the max_dvga_gain value. this will reduce power consumption in t he receiver front end, since the highest gain settings are avoided. the magn_target setting is a compromise between blocker tolerance/selectivity and sensitivity. the value sets the desired signal level in the channel into the demodulator. increasing this value reduces the headroom for blockers, and therefore close-in selectivity. 15.10.6 cs relative threshold the relative threshold detects sudden changes in the measured signal level. this setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. the register field agcctrl1.carrier_sense_rel_thr is used to enable/disable relative cs, and to select threshold of 6 db, 10 db or 14 db rssi change. 15.10.7 clear channel assessment (cca) the clear channel assessment is used to indicate if the current channel is free or busy. the current cca state is viewable in the pktstatus register mcsm1.cca_mode selects the mode to use when determining cca. when the stx or sfstxon command strobe is given while CC2510FX/cc2511fx is in the rx state, the tx state is only entered if the clear
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 207 of 252 channel requirements are fulfilled. the chip will otherwise remain in rx. this feature is called tx if cca. four cca requirements can be programmed: ? always (cca disabled, always goes to tx) ? if rssi is below threshold ? unless currently receiving a packet ? both the above (rssi below threshold and not currently receiving a packet) 15.10.8 link quality indicator (lqi) the link quality indicator is a metric of the current quality of the received signal. if pktctrl1.append_status is enabled, the value is automatically appended to the end of each received packet. the value can also be read from the lqi status register. the lqi is calculated over the 64 symbols following the sync word (first 8 packet bytes). lqi is best used as a relative measurement of the link quality, since the value is dependent on the modulation format. 15.11 forward error correction with interleaving CC2510FX/cc2511fx has built-in support for forward error correction (fec). to enable this option, set mdmcfg1.fec_en to 1. fec is employed on the data field and crc word in order to reduce the gross bit error rate when operating near the se nsitivity limit. redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors. the use of fec allows correct reception at a lower snr, thus extending communication range. alternatively, for a given snr, using fec decreases the bit erro r rate (ber). as the packet error rate (per) is related to ber by: length packet ber per _ ) 1 ( 1 ? ? = , a lower ber can be used to allow significantly longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. finally, in realistic ism radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. fec will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors). the fec scheme adopted for CC2510FX/cc2511fx is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m -bit window). the convolutional coder is a rate 1/2 code with a constraint length of m=4. the coder codes one input bit and produces two output bits; hence, the effective data rate is halved. 15.11.1 interleaving data received through real radio channels will often experience burst errors due to interference and time-varying signal strengths. in order to increase the robustness to errors spanning multiple bits, interleaving is used when fec is enabled. after de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. CC2510FX/cc2511fx employs matrix interleaving, which is illustrated in figure 49. the on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. in the transm itter, the data bits are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix and fed to the rate ? convolutional coder. conversely, in the receiver, the received symbols are written into the columns of the matrix, whereas the data passed onto the convolutional decoder is read from the rows of the matrix. when fec and interleaving is used at least one extra byte is required for trellis termination. in addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). the packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. note that t hese extra bytes are invisible to the user, as they are removed before the received packet enters the rfd data register. when fec and interleaving is used the minimum data payload is 2 bytes in fixed and variable packet length mode.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 208 of 252 receiver transmitter 1) storing coded data 2) transmitting interleaved data 4) passing on data to decoder 3) receiving interleaved data tx data demodulator modulator encoder rx data decoder figure 49: general principle of matrix interleaving 15.12 radio control CC2510FX/cc2511fx has a built-in state machine that is used to switch between different operation states (modes). the change of state is done by using command strobes. a simplified state diagram, together with typical usage and current consumption, is shown in figure 43 on page 192. the complete radio control state diagram is shown in figure 50. the numbers refer to the state number readable in the marcstate status register. this register is primarily for test purposes.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 209 of 252 figure 50: complete radio control state diagram 15.12.1 active modes the CC2510FX/cc2511fx radio has two active modes: receive and transmit. these modes are activated directly by the cpu by writing the srx and stx command strobes to the rfst register. the frequency synthesizer must be calibrated regularly. CC2510FX/cc2511fx has one manual calibration option (using the scal strobe), and three automatic calib ration options. the automatic calibration op tions are controlled by the mcsm0.fs_autocal setting: ? calibrate when going from idle to either rx or tx (or fstxon) ? calibrate when going from either rx or tx to idle
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 210 of 252 ? calibrate every fourth time when going from either rx or tx to idle the calibration takes a constant number of xosc cycles (see table 66 for timing details). when rx is activated, the chip will remain in receive mode until the rx termination timer expires (see section 15.12.3) or a packet has been successfully received. note: the probability that a false sync word is detected can be reduced by using pqt, cs, maximum sync word length and sync word qualifier mode as describe in section 15.10. after a packet is successfully received t he radio controller will then go to the state indicated by the mcsm1.rxoff_mode setting. the possible states are: ? idle ? fstxon: frequency synthesizer on and ready at the tx frequency. activate tx with stx . ? tx: start sending preambles ? rx: start search for a new packet similarly, when tx is active the chip will remain in the tx state until the current packet has been successfully transmitted. then the state will change as indicated by the mcsm1.txoff_mode setting. the possible destinations are the same as for rx. the cpu can change the state from rx to tx and vice versa by using the command strobes. if the radio controller is currently in transmit and the srx strobe is written, the current transmission will be ended and the transition to rx will be done. if the radio controller is in rx when the stx or sfstxon command strobes are issued, the ?tx if clear channel? function will be used. if the channel is not clear, the chip will remain in rx. the mcsm1.cca_mode setting controls the conditions for clear channel assessment. see section 15.10.7 on page 206 for details. the sidle command strobe can always be issued to force the radio controller to go to the idle state. 15.12.2 timing the radio controller controls most timing in CC2510FX/cc2511fx , such as synthesizer calibration, pll lock and rt/tx turnaround times. timing from idle to rx and idle to tx is constant, dependent on the auto calibration setting. rx/tx and tx/rx turnaround times are constant. the calibration time is constant 18739 clock periods. table 66 shows timing in crystal clock cycles for key state transitions. power on time and xosc start-up times are variable, but within the limits stated in table 9. note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 s to approximately 150 s. this is explained in section 15.18.2. description xosc periods 26mhz crystal idle to rx, no calibration 2298 88.4s idle to rx, with calibration ~21037 809s idle to tx/fstxon, no calibration 2298 88.4s idle to tx/fstxon, with calibration ~21037 809s tx to rx switch 560 21.5s rx to tx switch 250 9.6s rx or tx to idle, no calibration 2 0.1s rx or tx to idle, with calibration ~18739 721s manual calibration ~18739 721s table 66: state transition timing 15.12.3 rx termination timer CC2510FX/cc2511fx has optional functions for automatic termination of rx after a programmable time. the termination timer starts when enabling the demodulator. the timeout is programmable with the mcsm2.rx_time setting. when the timer expires, the radio co ntroller will check the condition for staying in rx; if the condition is not met, rx will terminate. after the timeout, the condition will be checked continuously. the programmable conditions are: ? mcsm2.rx_time_qual=0 : continue receive if sync word has been found ? mcsm2.rx_time_qual=1 : continue receive if sync word has been found or preamble quality is above threshold (pqt) if the system can expect the transmission to have started when enabling the receiver, the mcsm2.rx_time_rssi function can be used. the radio controller will then terminate rx if the first valid carrier sense sample indicates no carrier (rssi below threshold). see section
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 211 of 252 15.10.4 on page 205 for details on carrier sense. for ook modulation, lack of carrier sense is only considered valid after eight symbol periods. thus, the mcsm2.rx_time_rssi function can be used in ook mode when the distance between ?1? symbols is 8 or less. if rx terminates due to no carrier sense when the mcsm2.rx_time_rssi function is used, or if no sync word was found when using the mcsm2.rx_time timeout function, the chip will always go back to idle. otherwise, the mcsm1.rxoff_mode setting determines the state to go to when rx ends. 15.13 frequency programming the frequency programming in CC2510FX/cc2511fx is designed to minimize the programming needed in a channel-oriented system. to set up a system with channel numbers, the desired channel spacing is programmed with the mdmcfg0.chanspc_m and mdmcfg1.chanspc_e registers. the channel spacing registers are mantissa and exponent respectively. the base or start frequency is set by the 24 bit frequency word located in the freq2 , freq1 and freq0 registers. this word will typically be set to the centre of the lowest channel frequency that is to be used. the desired channel number is programmed with the 8-bit channel number register, channr.chan , which is multiplied by the channel offset. the resultant carrier frequency is given by: () () 2 _ 16 2 ) _ 256 ( 2 ? ? + ? + ? = e chanspc xosc carrier m chanspc chan freq f f with a 26 mhz crystal the maximum channel spacing is 405 khz. to get e.g. 1 mhz channel spacing one solution is to use 333 khz channel spacing and select each third channel in channr.chan . the preferred if frequency is programmed with the fsctrl1.freq_if register. the if frequency is given by: if freq f f xosc if _ 2 10 ? = note that the smartrf ? studio software automatically calculates the optimum fsctrl1.freq_if register setting based on channel spacing and channel filter bandwidth. if any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. hence, the frequency programming should only be updated when the radio is in the idle state. 15.14 vco the vco is completely integrated on-chip. 15.14.1 vco and pll self-calibration the vco characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. in order to ensure reliable operation, CC2510FX/cc2511fx includes frequency synthesizer self-calibration circuitry. this calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). the number of xosc cycles for completing the pll calibration is given in table 66 on page 210. the calibration can be initiated automatically or manually. the synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off. this is configured with the mcsm0.fs_autocal register setting. in manual mode, the calibration is initiated when the scal command strobe is activated in the idle mode. note that the calibration values are maintained in power-down modes pm2/3, so the calibration is still valid after waking up from these power-down modes (unless supply voltage or temperature has changed significantly).
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 212 of 252 15.15 output power programming the rf output power level from the device has two levels of programmabi lity, as illustrated in figure 51. firstly, the pa_table7- pa_table0 registers can hold up to eight user selected output power settings. secondly, the 3-bit frend0.pa_power value selects which pa_table7-0 register to use. this two-level functionality provides flexible pa power ramp up and ramp down at the start and end of transmission. in each case, all the pa power settings from pa_table from index 0 up to the frend0.pa_power value are used. the power ramping at the start and at the end of a packet can be turned off by setting frend0.pa_power to zero and then programming the desired output power in pa_table0 . table 67 contains recommended pa_table settings for various output levels and frequency bands, together with current consumption in the rf transceiver. e.g 6 pa_power[2:0] in frend0 register pa_table0[7:0] pa_table1[7:0] pa_table2[7:0] pa_table3[7:0] pa_table4[7:0] pa_table5[7:0] pa_table6[7:0] pa_table7[7:0] index into pa_table7-0 the pa uses this setting. settings 0 to pa_power are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ook modulation. the smartrf? studio software should be used to get optimum patable settings for various output powers. figure 51: pa_power and pa_table7-0
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 213 of 252 output power [dbm] typical +25 oc, 3.0 v setting current consumption, typ. [ma] (?55 or less) 0x00 8.9 ?30 0x44 10.1 ?28 0x41 10.0 ?26 0x4c 11.7 ?24 0x53 11.1 ?22 0x83 10.9 ?20 0x46 10.5 ?18 0x4a 11.7 ?16 0x86 11.0 ?14 0x66 12.9 ?12 0xc6 11.5 ?10 0x69 14.1 ?8 0x99 13.6 ?6 0x7f 15.4 ?4 0xaa 16.7 ?2 0xbf 18.5 0 0xfb 21.6 1 0xff 21.9 table 67: optimum pa_table settings for various output power levels (subject to changes) 15.16 selectivity graphs figure 52 to figure 56 show the typical sele ctivity performance (adjacent and alternate rejection). -10 0 10 20 30 40 50 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 frequency offset [mhz] selectivity [db] figure 52: typical selectivity at 2.4 kbps. if frequency is 273.9 khz. mdmcfg2.dem_dcfilt_off = 1
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 214 of 252 -10 -5 0 5 10 15 20 25 30 35 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 frequency offset [m hz] selectivity [db] figure 53: typical selectivity at 10 kbps. if frequency is 273.9 khz. mdmcfg2.dem_dcfilt_off = 1 -20 -10 0 10 20 30 40 50 -3 -2 -1 0 1 2 3 frequency offset [mhz] selectivity [db] figure 54: typical selectivity at 250 kbps. if frequency is 177.7 khz. mdmcfg2.dem_dcfilt_off = 0 -20 -10 0 10 20 30 40 50 -3 -2 -1 0 1 2 3 frequency offset [mhz] selectivity [db] figure 55: typical selectivity at 250 kbps. if frequency is 457 khz. mdmcfg2.dem_dcfilt_off = 1
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 215 of 252 -20 -15 -10 -5 0 5 10 15 20 25 30 35 -3 -2 -1 0 1 2 3 frequency offset [mhz] selectivity [db] figure 56: typical selectivity at 500 kbps. if frequency is 307.4 khz. mdmcfg2.dem_dcfilt_off = 0
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 216 of 252 15.17 antenna interface the balanced rf input and output of CC2510FX/cc2511fx share two common pins and are designed for a simple, low-cost matching and balun network on the printed circuit board. the receive- and transmit switching at the CC2510FX/cc2511fx front-end is controlled by a dedicated on-chip function, eliminating the need for an external rx/tx-switch. a few passive external components combined with the internal rx/tx switch/termination circuitry ensures match in both rx and tx mode. although CC2510FX/cc2511fx has a balanced rf input/output, the chip can be connected to a single-ended antenna with few external low cost capacitors and inductors. the passive matching/filtering network connected to CC2510FX/cc2511fx should have the following differential impedance as seen from the rf-port (rf_p and rf_n) towards the antenna: z out = 80 + j74 ? to ensure optimal matching of the CC2510FX/cc2511fx differential output it is recommended to follow the cc2510em reference designs as closely as possible. gerber files for the reference designs are available for download from the chipcon website . 15.18 system considerations and guidelines 15.18.1 srd regulations international regulations and national laws regulate the use of radio receivers and transmitters. short range devices (srds) for license free operation are allowed to operate in the 2.45 ghz bands worldwide. the most important regulations are en 300 440 and en 300 328 (europe), fcc cfr47 part 15.247 and 15.249 (usa), and arib std-t66 (japan). a summary of the most important aspects of these regulations can be found in application note an032 srd regulations for license-free transceiver operation in the 2.4 ghz band , available from the chipcon website. please note that compliance with regulations is dependent on complete system performance. it is the customer?s responsibility to ensure that the system complies with regulations. 15.18.2 frequency hopping and multi-channel systems the 2.400 ? 2.4835 ghz band is shared by many systems both in industrial, office and home environments. it is therefore recommended to use frequency hopping spread spectrum (fhss) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. fhss also combats multipath fading. CC2510FX/cc2511fx is highly suited for fhss or multi-channel systems due to its agile frequency synthesizer and effective communication interface. using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller. charge pump current, vco current and vco capacitance array calibration data is required for each frequency when implementing frequency hopping for CC2510FX/cc2511fx . there are 3 ways of obtaining the calibration data from the chip: 1) frequency hopping with calibration for each hop. the pll calibration time is approximately 720 s. 2) fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting fscal3 , fscal2 and fscal1 register values in mcu memory. between each frequency hop, the calibration process can then be replaced by writing the fscal3 , fscal2 and fscal1 register values corresponding to the next rf frequency. the pll turn on time is approximately 90 s. 3) run calibration on a single frequency at startup. next write 0hex to fscal3[5:4] to disable the charge pump calibration. after writing to fscal3[5:4] strobe srx (or stx ) with mcsm0.fs_autocal = 1 for each new frequency hop. that is, vco current and vco capacitance calibration is done but not charge pump current calibration. when charge pump current calibration is disabled the calibration time is reduced from approximately 720 s to approximately 150 s.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 217 of 252 there is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. solution 3) gives approximately 570 s smaller blanking interval than solution 1). 15.18.3 wideband modulation not using spread spectrum digital modulation systems under fcc part 15.247 includes fsk and gfsk modulation. a maximum peak output power of +30 dbm is allowed if the 6 db bandwidth of the modulated signal is not less than 500 khz. in addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dbm in any 3 khz band. operating at high data rates and high frequency separation, the cc2500 is suited for systems targeting compliance with digital modulation system as defined by fcc part 15.247. an external power amplifier is needed to increase the output above +0 dbm. 15.18.4 data burst transmissions the high maximum data rate of CC2510FX/cc2511fx opens up for burst transmissions. a low average data rate link (say 10 kbps), can be realized using a higher over-the-air data rate. buffering the data and transmitting in bursts at high data rate (say 500 kbps) will reduce the time in active mode, and hence also reduce the average current consumption significantly. reducing the time in active mode will reduce the likelihood of collisions with other systems, e.g. wlan. 15.18.5 continuous transmissions in data streaming applications the CC2510FX/cc2511fx opens up for continuous transmissions at 500 kbps effective data rate. as the modulation is done with an i/q up- converter with lo i/q-signals coming from a closed loop pll, there is no limitation in the length of a transmission. (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate.) 15.18.6 crystal drift compensation the CC2510FX/cc2511fx has a very fine frequency resolution. this feature can be used to compensate for frequ ency offset and drift. the frequency offset between an ?external? transmitter and the receiver is measured in the CC2510FX/cc2511fx and can be read back from the freqest status register. the measured frequency offset can be used to calibrate the frequency using the ?external? transmitter as the reference. that is, the received signal of the device will match the receiver?s channel filter better. in the same way the centre frequency of the transmitted signal will match the ?external? transmitter?s signal. 15.18.7 spectrum efficient modulation CC2510FX/cc2511fx also has the possibility to use gaussian shaped fsk (gfsk). this spectrum-shaping feature improves adjacent channel power (acp) and occupied bandwidth. in ?true? fsk systems with abrupt frequency shifting, the spectrum is inherently broad. by making the frequency shift ?softer?, the spectrum can be made significantly narrower. thus, higher data rates can be transmitted in the same bandwidth using gfsk. 15.18.8 low cost systems as the CC2510FX/cc2511fx provides 500 kbps multi-channel performance without any external filters, a very low cost system can be made. a differential antenna will eliminate the need for a balun, and the dc biasing can be achieved in the antenna topology, see figure 7. a hc-49 type smd crystal is used in the CC2510FX em reference design. note that the crystal package strongly influences the price. in a size constrained pcb design a smaller, but more expensive, crystal may be used. 15.18.9 battery operated systems in low power applications, the low power modes pm2 or pm3 with should be used when the CC2510FX/cc2511fx is not active. the sleep timer wake-on-radio functionality should be used in low power applications. 15.18.10 increasing output power in some applications it may be necessary to extend the link range. adding an external power amplifier is the most effective way of doing this. the power amplifier should be inserted between the antenna and the balun, and two
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 218 of 252 t/r switches are needed to disconnect the pa in rx mode. see error! reference source not found. . figure 57. block diagram of CC2510FX/cc2511fx usage with external power amplifier cc2510 f x/cc251 balun filte r a ntenna t/r switch t/r switch pa
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 219 of 252 15.19 radio registers this section describes all rf registers used for control and status for the radio. the rf registers reside in xdata memory space in the region 0xdf00-0xdf3d. table 68 gives an overview of register addresses while the remaining tables in this section describe each register.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 220 of 252 xdata address register description 0xdf00 sync1 sync word, high byte 0xdf01 sync0 sync word, low byte 0xdf02 pktlen packet length 0xdf03 pktctrl1 packet automation control 0xdf04 pktctrl0 packet automation control 0xdf05 addr device address 0xdf06 channr channel number 0xdf07 fsctrl1 frequency synthesizer control 0xdf08 fsctrl0 frequency synthesizer control 0xdf09 freq2 frequency control word, high byte 0xdf0a freq1 frequency c ontrol word, middle byte 0xdf0b freq0 frequency control word, low byte 0xdf0c mdmcfg4 modem configuration 0xdf0d mdmcfg3 modem configuration 0xdf0e mdmcfg2 modem configuration 0xdf0f mdmcfg1 modem configuration 0xdf10 mdmcfg0 modem configuration 0xdf11 deviatn modem deviation setting 0xdf12 mcsm2 main radio control state machine configuration 0xdf13 mcsm1 main radio control state machine configuration 0xdf14 mcsm0 main radio control state machine configuration 0xdf15 foccfg frequency offs et compensation configuration 0xdf16 bscfg bit sync hronization configuration 0xdf17 agctrl2 agc control 0xdf18 agctrl1 agc control 0xdf19 agctrl0 agc control 0xdf1a frend1 front end rx configuration 0xdf1b frend0 front end tx configuration 0xdf1c fscal3 frequency synthesizer calibration 0xdf1d fscal2 frequency synthesizer calibration 0xdf1e fscal1 frequency synthesizer calibration 0xdf1f fscal0 frequency synthesizer calibration 0xdf20 - reserved 0xdf21 - reserved 0xdf22 - reserved 0xdf23 - reserved 0xdf24 - reserved 0xdf25 - reserved 0xdf27 pa_table7 pa output power setting 0xdf28 pa_table6 pa output power setting 0xdf29 pa_table5 pa output power setting 0xdf2a pa_table4 pa output power setting 0xdf2b pa_table3 pa output power setting 0xdf2c pa_table2 pa output power setting 0xdf2d pa_table1 pa output power setting 0xdf2e pa_table0 pa output power setting 0xdf2f iocfg2 gdo2 output pin configuration 0xdf30 iocfg1 gdo1 output pin configuration 0xdf31 iocfg0 gdo0 output pin configuration
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 221 of 252 xdata address register description 0xdf36 partnum chip identifier 0xdf37 version configuration 0xdf38 freqest frequency offset estimate 0xdf39 lqi link quality indicator 0xdf3a rssi received signal strength indication 0xdf3b marcstate main radio control state 0xdf3c pkstatus packet status 0xdf3d vco_vc_dac pll calibration current table 68: overview of rf registers 0xdf2f: iocfg2 ? gdo2 output pin configuration bit field name reset r/w description 7 - r0 reserved 6 gdo2 _inv 0 r/w invert output, i.e. select active low / high 5:0 gdo2 _cfg[5:0] 0x00 r/w debug output on p1_7 pin. see table 69 for description of internal signals which can be output on this pin for debug purpose 0xdf30: iocfg1 ? gdo1 output pin configuration bit field name reset r/w description 7 gdo_ds 0 r/w set high (1) or low (0) output drive strength on the gdo pins. 6 gdo1 _inv 0 r/w invert output, i.e. select active low / high 5:0 gdo1 _cfg[5:0] 0x00 r/w debug output on p1_6 pin. see table 69 for description of internal signals which can be output on this pin for debug purpose 0xdf31: iocfg0 ? gdo0 output pin configuration bit field name reset r/w description 7 temp_sensor_enable 0 r/w enable analog temperature sensor. write 0 in all other register bits when using temperature sensor. 6 gdo0 _inv 0 r/w invert output, i.e. select active low / high 5:0 gdo0 _cfg[5:0] 0x00 r/w debug output on p1_5 pin. see table 69 for description of internal signals which can be output on this pin for debug purpose 0xdf00: sync1 ? sync word, high byte bit field name reset r/w description 7:0 sync[15:8] 0xd3 r/w 8 msb of 16-bit sync word
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 222 of 252 0xdf01: sync0 ? sync word, low byte bit field name reset r/w description 7:0 sync[7:0] 0x91 r/w 8 lsb of 16-bit sync word 0xdf02: pktlen ? packet length bit field name reset r/w description 7:0 packet_length 0xff r/w indicates the packet length when fixed length packets are enabled. if va riable length packets are used, this value indicates the maximum length packets allowed. 0xdf03: pktctrl1 ? packet automation control bit field name reset r/w description 7:5 pqt[2:0] 000 r/w preamble quality estim ator threshold. the preamble quality estimator increases an internal c ounter by one each time a bit is received that is different from the previous bit, and decreases the counter by 4 each time a bit is received that is the same as the last bit. the counter saturates at 0 and 31. a threshold of 4pqt for this counter is used to gate sync word detection. when pqt=0 a sync word is always accepted. 4:3 - 00 r0 reserved 2 append_status 1 r/w when enabled, two stat us bytes will be appended to the payload of the packet. the status bytes c ontain rssi and lqi values, as well as the crc ok flag. 1:0 adr_chk[1:0] 00 r/w controls address c heck configuration of received packages. setting address check configuration 0 (00) no address check 1 (01) address check, no broadcast 2 (10) address check, 0 (0x00) broadcast 3 (11) address check, 0 (0x00) and 255 (0xff) broadcast
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 223 of 252 0xdf04: pktctrl0 ? packet automation control bit field name reset r/w description 7 - 0 r0 reserved 6 white_data 1 r/w turn data whitening on / off 0: whitening off 1: whitening on data whitening can only be used when p ktctrl0.cc2400_en = 0 (default). 5:4 pkt_format[1:0] 00 r/w format of rx and tx data setting packet format 0 (00) normal mode, use fifos for rx and tx 1 (01) serial synchronous mode, used for backwards compatibility 2 (10) random tx mode; sends random data using pn9 generator. used for test. works as normal mode, setting 0 (00), in rx. 3 (11) asynchronous transparent mode. data in on gdo0 and data out on either of the gdo pins 3 cc2400_en 0 r/w enable cc2400 support. use same crc implementation as cc2400. pktctrl0.white_data must be 0 if pktctrl0.cc2400_en = 1. 2 crc_en 1 r/w 1: crc calculation in tx and crc check in rx enabled 0: crc disabled for tx and rx 1:0 length_config[1:0] 01 r/w configure the packet length setting packet length configuration 0 (00) fixed length pack ets, length configured in pktlen register 1 (01) variable length pack ets, packet length configured by the first byte after sync word 2 (10) enable infinite length packets 3 (11) reserved 0xdf05: addr ? device address bit field name reset r/w description 7:0 device_addr[7:0] 0x00 r/w address used for packet filtration. optional broadcast addresses are 0 (0x00) and 255 (0xff). 0xdf06: channr ? ch annel number bit field name reset r/w description 7:0 chan[7:0] 0x00 r/w the 8-bit unsigned c hannel number, which is multiplied by the channel spacing setting and added to the base frequency.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 224 of 252 0xdf07: fsctrl1 ? frequency synthesizer control bit field name reset r/w description 7:5 - 000 r0 not used 4:0 freq_if[4:0] 01111 r/w the desired if frequency to employ in rx. subtracted from fs base frequency in rx and controls the digital complex mixer in the demodulator. if freq f f xosc if _ 2 10 ? = the default value gives an if frequency of 381khz, assuming a 26.0mhz crystal. 0xdf08: fsctrl0 ? frequency synthesizer control bit field name reset r/w description 7:0 freqoff[7:0] 0x00 r/w frequency offset added to the base frequency before being used by the fs. (2-complement). resolution is f xtal /2 14 (1.5khz-1.7khz); range is 186khz to 217khz, dependent of xtal frequency. the safc strobe command and the automatic afc mechanism add the current freqest value to freqoff. 0xdf09: freq2 ? frequency control word, high byte bit field name reset r/w description 7:6 freq[23:22] 00 r freq[23:22] is always binary 01 (the freq2 register is in the range 85 to 95 with 26mhz-28mhz crystal) 5:0 freq[21:16] 0x1e r/w freq[23:0] is the base frequency for the frequency synthesizer in increments of f xosc /2 16 . [] 0 : 23 2 16 freq f f xosc carrier ? = the default frequency word gives a base frequency of 2464mhz, assuming a 26.0mhz crystal. with the default channel spacing settings, the following freq2 values and channel numbers can be used: freq2 base frequency frequency range (chan numbers) 91 (0x5b) 2386mhz 2400.2mhz-2437mhz (71-255) 92 (0x5c) 2412mhz 2412mhz-2463mhz (0-255) 93 (0x5d) 2438mhz 2431mhz-2483.4mhz (0-227) 94 (0x5e) 2464mhz 2464mhz-2483.4mhz (0-97) 0xdf0a: freq1 ? frequency control word, middle byte bit field name reset r/w description 7:0 freq[15:8] 0xc4 r/w ref. freq2 register
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 225 of 252 0xdf0b: freq0 ? frequency control word, low byte bit field name reset r/w description 7:0 freq[7:0] 0xec r/w ref. freq2 register 0xdf0c: mdmcfg4 ? modem configuration bit field name reset r/w description 7:6 chanbw_e[1:0] 10 r/w 5:4 chanbw_m[1:0] 00 r/w sets the decimation ratio for the delta-sigma adc input stream and thus the channel bandwidth. e chanbw xosc channel m chanbw f bw _ 2 ) _ 4 ( 8 + ? = the default values give 203khz channel filter bandwidth, assuming a 26.0mhz crystal. 3:0 drate_e[3:0] 1100 r/w the exponent of the user specified symbol rate 0xdf0d: mdmcfg3 ? modem configuration bit field name reset r/w description 7:0 drate_m[7:0] 0x22 r/w the mantissa of the us er specified symbol rate. the symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. the 9 th bit is a hidden ?1?. the resulting data rate is: ( ) xosc e drate data f m drate r ? ? + = 28 _ 2 2 _ 256 the default values give a data rate of 115.051kbps (closest setting to 115.2kbps), assu ming a 26.0mhz crystal.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 226 of 252 0xdf0e: mdmcfg2 ? modem configuration bit field name reset r/w description 7 dem_dcfilt_off 0 r/w disable digital dc blocking filter before demodulator. 0 = enable (better sensitivity for data rates 250 kbps) 1 = disable (reduced power consumption) the recommended if frequency changes when the dc blocking is disabled. 6:4 mod_format[2:0] 000 r/w the modulation format of the radio signal setting modulation format 0 (000) 2-fsk 1 (001) gfsk 2 (010) - 3 (011) ook 4 (100) - 5 (101) - 6 (110) - 7 (111) msk 3 manchester_en 0 r/w enables manchester encoding/decoding. 0 = disable 1 = enable 2:0 sync_mode[2:0] 010 r/w combined sync-word qualifier mode. the values 0 (000) and 4 (100) disables sync word transmission in tx and sync word detection in rx. the values 1 (001), 2 (001), 5 (101) and 6 (110) enables 16-bit sync word transmission in tx and 16- bits sync word detection in rx. only 15 of 16 bits need to match in rx when using setting 1 (001) or 5 (101). the values 3 (011) and 7 (111) enables repeated sync word transmission in rx and 32-bits sync word detection in rx (only 30 of 32 bits need to match). setting sync-word qualifier mode 0 (000) no preamble/sync 1 (001) 15/16 sync word bits detected 2 (010) 16/16 sync word bits detected 3 (011) 30/32 sync word bits detected 4 (100) no preamble/sync, carrier-sense above threshold 5 (101) 15/16 + carrier-sense above threshold 6 (110) 16/16 + carrier-sense above threshold 7 (111) 30/32 + carrier-sense above threshold
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 227 of 252 0xdf0f: mdmcfg1 ? modem configuration bit field name reset r/w description 7 fec_en 0 r/w enable forward error co rrection (fec) with interleaving for packet payload 0 = disable 1 = enable 6:4 num_preamble[2:0] 010 r/w sets the minimum number of preamble bytes to be transmitted setting number of preamble bytes 0 (000) 2 1 (001) 3 2 (010) 4 3 (011) 6 4 (100) 8 5 (101) 12 6 (110) 16 7 (111) 24 3:2 - 0 r0 reserved 1:0 chanspc_e[1:0] 10 r/w 2 bit exponent of channel spacing 0xdf10: mdmcfg0 ? modem configuration bit field name reset r/w description 7:0 chanspc_m[7:0] 0xf8 r/w 8-bit mantissa of channel spacing (initi al 1 assumed). the channel spacing is multiplied by the channel number chan and added to the base frequency. it is unsigned and has the format: () chan m chanspc f f e chanspc xosc channel ? ? + ? = ? _ 18 2 _ 256 2 the default values give 199.951k hz channel spacing (the closest setting to 200khz), assuming 26.0mhz crystal frequency.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 228 of 252 0xdf11: deviatn ? modem deviation setting bit field name reset r/w description 7 - 0 r0 reserved 6:4 deviation_e[2:0] 100 r/w deviation exponent 3 - 0 r0 reserved 2:0 deviation_m[2:0] 111 r/w when msk modulation is enabled: sets fraction of symbol period used for phase change. when fsk modulation is enabled: deviation mantissa, interpreted as a 4-bit value with msb implicit 1. the resulting fsk deviation is given by: e deviation xosc dev m deviation f f _ 17 2 ) _ 8 ( 2 ? + ? = the default values give 47.607khz deviation, assuming 26.0mhz crystal frequency.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 229 of 252 0xdf12: mcsm2 ? main radio control state machine configuration bit field name reset r/w description 7:5 reserved r0 reserved 4 rx_time_rssi 0 r/w direct rx termin ation based on rssi measurement (carrier sense). for ook modulation, rx times out if there is no carrier sense in the fi rst 8 symbol periods. 3 rx_time_qual 0 r/w when the rx_time timer expires the chip stays in rx mode if sync word is found when rx_time_qual=0, or either sync word is found or pqt is set when rx_time_qual=1. 2:0 rx_time[2:0] 7 (111) r/w timeout for sync word search in rx. the timeout is relative to the programmed event0 timeout, which means that the duty cycle can be set in wake-on-radio (wor) mode. the rx timeout in s is given by event0c(rx_time, wor_res), w here c is given by the table below (xosc = 26 mhz): rx_time[2:0] wor_res = 0 wor_res = 1 wor_res = 2 wor_res = 3 0 (000) 3.6058 18.0288 32.4519 46.8750 1 (001) 1.8029 9.0144 16.2260 23.4375 2 (010) 0.9014 4.5072 8.1130 11.7188 3 (011) 0.4507 2.2536 4.0565 5.8594 4 (100) 0.2254 1.1268 2.0282 2.9297 5 (101) 0.1127 0.5634 1.0141 1.4648 6 (110) 0.0563 0.2817 0.5071 0.7324 7 (111) until end of packet as an example, event0 = 34666, wor_res = 0 and rx _time = 6 corresponds to 1.96 ms rx timeout, 1 s polling interval and 0.195% duty cycle. note that wor_res should be 0 or 1 when using wor. the duty cycle is approximated by: rx_time[2:0] wor_res = 0 wor_res = 1 0 (000) 12.50% 1.95% 1 (001) 6.250% 9765ppm 2 (010) 3.125% 4883ppm 3 (011) 1.563% 2441ppm 4 (100) 0.781% na 5 (101) 0.391% na 6 (110) 0.195% na 7 (111) until end of packet note that the rc oscillator must be enabled in order to us e setting 0-6, because the ti meout counts rc oscillator periods. wor mode does not need to be enabled. the timeout counter resolution is limited: with rx_time=0 , the timeout count is given by the 13 msbs of event0, decreasing to the 7 msbs of event0 with rx_time=6 .
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 230 of 252 0xdf13: mcsm1 ? main radio control state machine configuration bit field name reset r/w description 7:6 - 00 r0 reserved 5:4 cca_mode[1:0] 11 r/w selects cca_mode; reflected in cca signal setting clear channel indication 0 (00) always 1 (01) if rssi below threshold 2 (10) unless currently receiving a packet 3 (11) if rssi below threshold unless currently receiving a packet 3:2 rxoff_mode[1:0] 00 r/w select what should happen when a packet has been received setting next state after fi nishing packet reception 0 (00) idle 1 (01) fstxon 2 (10) tx 3 (11) stay in rx 1:0 txoff_mode[1:0] 00 r/w select what should happen when a packet has been sent (tx) setting next state after fi nishing packet transmission 0 (00) idle 1 (01) fstxon 2 (10) stay in tx (start sending preamble) 3 (11) rx 0xdf14: mcsm0 ? main radio control state machine configuration bit field name reset r/w description 7:6 - 00 r0 reserved 5:4 fs_autocal[1:0] 00 r/w automatically calibrate when going to rx or tx, or back to idle setting when to perform automatic calibration 0 (00) never (manually calibrate using scal strobe) 1 (01) when going from idle to rx or tx (or fstxon) 2 (10) when going from rx or tx back to idle 3 (11) every 4 th time when going from rx or tx to idle in some automatic wake-on-radi o (wor) applications, using setting 3 (11) can signific antly reduce current consumption. 3:0 - 0100 r reserved
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 231 of 252 0xdf15: foccfg ? frequency offset compensation configuration bit field name reset r/w description 7:6 reserved r0 5 foc_bs_cs_gate 1 r/w if set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the carrier_sense signal goes high. 4:3 foc_pre_k[1:0] 2 (10) r/w the frequency compensation loop gain to be used before a sync word is detected. setting freq. compensation loop gain before sync word 0 (00) k 1 (01) 2 k 2 (10) 3 k 3 (11) 4 k 2 foc_post_k 1 r/w the frequency com pensation loop gain to be used after a sync word is detected. setting freq. compensation loop gain after sync word 0 same as foc_pre_k 1 k /2 1:0 foc_limit[1:0] 2 (10) r/w the saturati on point for the frequency offset compensation algorithm: setting saturation point (max compensated offset) 0 (00) 0 (no frequency offset compensation) 1 (01) bw chan /8 2 (10) bw chan /4 3 (11) bw chan /2 frequency offset compensation is not supported for ook; always use foc_limit=0 with this modulation format.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 232 of 252 0xdf16: bscfg ? bit synchronization configuration bit field name reset r/w description 7:6 bs_pre_ki[1:0] 1 (01) r/w the clock recove ry feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): setting clock recovery loop integral gain before sync word 0 (00) k i 1 (01) 2 k i 2 (10) 3 k i 3 (11) 4 k i 5:4 bs_pre_kp[1:0] 2 (10) r/w the clock reco very feedback loop proportional gain to be used before a sync word is detected. setting clock recovery loop proportional gain before sync word 0 (00) k p 1 (01) 2 k p 2 (10) 3 k p 3 (11) 4 k p 3 bs_post_ki 1 r/w the clock recovery feedback loop integral gain to be used after a sync word is detected. setting clock recovery loop integral gain after sync word 0 same as bs_pre_ki 1 k i /2 2 bs_post_kp 1 r/w the clock recovery feedback loop proportional gain to be used after a sync word is detected. setting clock recovery loop proportional gain after sync word 0 same as bs_pre_kp 1 k p 1:0 bs_limit[1:0] 0 (00) r/w the saturation point for the data rate offset compensation algorithm: setting data rate offset saturation (max data rate difference) 0 (00) 0 (no data rate offset compensation performed) 1 (01) 3.125% data rate offset 2 (10) 6.25% data rate offset 3 (11) 12.5% data rate offset
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 233 of 252 0xdf17: agcctrl2 ? agc control bit field name reset r/w description 7: 6 max_dvga_gain[1:0] 0 (00) r/w reduces the maximum allowable dvga gain. setting allowable dvga settings 0 (00) all gain settings can be used 1 (01) the highest gai n setting can not be used 2 (10) the 2 highest gai n settings can not be used 3 (11) the 3 highest gai n settings can not be used 5: 3 max_lna_gain[2:0] 0 (000) r/w sets the maximum allowable lna + lna 2 gain relative to the maximum possible gain. setting maximum allowable lna + lna 2 gain 0 (000) maximum possible lna + lna 2 gain 1 (001) approx. 2.6 db below maximum possible gain 2 (010) approx. 6.1 db below maximum possible gain 3 (011) approx. 7.4 db below maximum possible gain 4 (100) approx. 9.2 db below maximum possible gain 5 (101) approx. 11.5 db below maximum possible gain 6 (110) approx. 14.6 db below maximum possible gain 7 (111) approx. 17.1 db below maximum possible gain 2: 0 magn_target[2:0] 3 (011) r/w these bits set the target value for the averaged amplitude from the digital channel filter (1 lsb = 0 db). setting target amplitude from channel filter 0 (000) 24 db 1 (001) 27 db 2 (010) 30 db 3 (011) 33 db 4 (100) 36 db 5 (101) 38 db 6 (110) 40 db 7 (111) 42 db
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 234 of 252 0xdf18: agcctrl1 ? agc control bit field name reset r/w description 7 reserved r0 6 agc_lna_priority 1 r/w selects between two different strategies for lna and lna 2 gain adjustment. when 1, the lna gain is decreased first. when 0, the lna 2 gain is decreased to minimum before decreasing lna gain. 5:4 carrier_sense_rel_thr[1:0] 0 (00) r/w sets the relative change threshold for asserting carrier sense setting carrier sense relative threshold 0 (00) relative carrier sense threshold disabled 1 (01) 6 db increase in rssi value 2 (10) 10 db increase in rssi value 3 (11) 14 db increase in rssi value 3:0 carrier_sense_abs_thr[3:0] 0 (0000) r/w sets the absolute rssi threshold for asserting carrier sense. the 2-complement signed threshold is programmed in steps of 1 db and is relative to the magn_target setting. setting carrier sens e absolute threshold (equal to channel filter amplitude when agc has not decreased gain) -8 (1000) absolute carrier sense threshold disabled -7 (1001) 7 db below magn_target setting ? ? -1 (1111) 1 db below magn_target setting 0 (0000) at magn_target setting 1 (0001) 1 db above magn_target setting ? ? 7 (0111) 7 db above magn_target setting
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 235 of 252 0xdf19: agcctrl0 ? agc control bit field name reset r/w description 7:6 hyst_level[1:0] 2 (10) r/w sets the leve l of hysteresis on the magnitude deviation (internal agc signal that determine gain changes). setting description 0 (00) no hysteresis, small symmetric dead zone, high gain 1 (01) low hysteresis, small asymmetric dead zone, medium gain 2 (10) medium hysteresis, medium asymmetric dead zone, medium gain 3 (11) large hysteresis, large asymmetric dead zone, low gain 5:4 wait_time[1:0] 1 (01) r/w sets the number of channel filter samples from a gain adjustment has been made until th e agc algorithm starts accumulating new samples. setting channel filter samples 0 (00) 8 1 (01) 16 2 (10) 24 3 (11) 32 3:2 agc_freeze[1:0] 0 (00) r/w control s when the agc gain should be frozen. setting function 0 (00) normal operation. always adjust gain when required. 1 (01) the gain setting is frozen when a sync word has been found. 2 (10) manually freeze the analog gain setting and continue to adjust the digital gain. 3 (11) manually freezes both the analog and the digital gain settings. used for m anually overriding the gain. 1:0 filter_length[1:0] 1 (01) r/w sets the aver aging length for the amplitude from the channel filter. setting channel filter samples 0 (00) 8 1 (01) 16 2 (10) 32 3 (11) 64 0xdf1a: frend1 ? front end rx configuration bit field name reset r/w description 7:6 lna_current[1:0] 1 (01) r/w adju sts front-end lna ptat current output 5:4 lna2mix_current[1:0] 1 (01) r/ w adjusts front-end ptat outputs 3:2 lodiv_buf_current_rx[1:0] 1 (01) r/w adjust s current in rx lo buffer (lo input to mixer) 1:0 mix_current[1:0] 2 (10) r/w adjusts current in mixer
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 236 of 252 0xdf1b: frend0 ? front end tx configuration bit field name reset r/w description 7:6 - 00 r0 reserved 5:4 lodiv_buf_ current _tx[1:0] 01 r/w adjusts current tx lo buffer (input to pa). the value to use in this field is given by the smartrf ? studio software. 3 - 0 r0 reserved 2:0 pa_power[2:0] 000 r/w selects pa power setting. this value is an index to the patable, which can be programmed with up to 8 different pa settings. the patab le settings from index ?0? to the pa_power value are used for power ramp- up/ramp-down at the start/end of transmission in all tx modulation formats. 0xdf1c: fscal3 ? frequency synthesizer calibration bit field name reset r/w description 7:6 fscal3[7:6] 2 (10) r/w frequency synthesizer calibration configuration. the value to write in this register before calibration is given by the smartrf ? studio software. 5:4 chp_curr_cal_en[1:0] 2 (10) r/w disabl e charge pump calibration stage when 0 3:0 fscal3[3:0] 9 (1001) r/w frequency synthesizer calibration result register. fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting fscal3, fscal2 and fs cal1 register values. between each frequency hop, calibration can be replaced by writing the fscal3, fscal2 and fscal1 regi ster values corresponding to the next rf frequency. 0xdf1d: fscal2 ? frequency synthesizer calibration bit field name reset r/w description 7:6 - 00 r0 reserved 5:0 fscal2[5:0] 0x0a r/w frequency synthesizer calibration result register. fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting fscal3, fscal2 and fs cal1 register values. between each frequency hop, calibration can be replaced by writing the fscal3, fscal2 and fscal1 regi ster values corresponding to the next rf frequency. 0xdf1e: fscal1 ? frequency synthesizer calibration bit field name reset r/w description 7:6 - 00 r0 reserved 5:0 fscal1[5:0] 0x02 r/w frequency synthesizer calibration result register. fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting fscal3, fscal2 and fs cal1 register values. between each frequency hop, calibration can be replaced by writing the fscal3, fscal2 and fscal1 regi ster values corresponding to the next rf frequency.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 237 of 252 0xdf1f: fscal0 ? frequency synthesizer calibration bit field name reset r/w description 7 - 0 r0 reserved 4:0 fscal0[6:0] 0x0d r/w frequency synthesizer calibration control. the value to use in this register is given by the smartrf ? studio software. 0xdf27: pa_table7 ? pa power setting 7 bit field name reset r/w description 7:0 pa_table7[7:0] 0x00 r/w power amplifier output power setting 7 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf28: pa_table6 ? pa power setting 6 bit field name reset r/w description 7:0 pa_table6[7:0] 0x00 r/w power amplifier output power setting 6 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf29: pa_table5 ? pa power setting 5 bit field name reset r/w description 7:0 pa_table5[7:0] 0x00 r/w power amplifier output power setting 5 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf2a: pa_table4 ? pa power setting 4 bit field name reset r/w description 7:0 pa_table4[7:0] 0x00 r/w power amplifier output power setting 4 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf2b: pa_table3 ? pa power setting 3 bit field name reset r/w description 7:0 pa_table3[7:0] 0x00 r/w power amplifier output power setting 3 currently used pa output power is selected by frend0.pa_power[2:0]
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 238 of 252 0xdf2c: pa_table2 ? pa power setting 2 bit field name reset r/w description 7:0 pa_table2[7:0] 0x00 r/w power amplifier output power setting 2 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf2d: pa_table1? pa power setting 1 bit field name reset r/w description 7:0 pa_table1[7:0] 0x00 r/w power amplifier output power setting 1 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf2e: pa_table0 ? pa power setting 0 bit field name reset r/w description 7:0 pa_table0[7:0] 0xc6 r/w power amplifier output power setting 0 currently used pa output power is selected by frend0.pa_power[2:0] 0xdf36: partnum ? chip identifier bit field name reset r/w description 7:0 partnum[7:0] 0x81 CC2510FX 0x91 cc2511fx r chip part number 0xdf37: version ? chip version bit field name reset r/w description 7:0 version[7:0] 0x03 r chip version number. 0xdf38: freqest ? frequency offset estimate from demodulator bit field name reset r/w description 7:0 freqoff_est r the estimated fr equency offset (two?s complement) of the carrier. resolution is f xtal /2 14 (1.5khz-1.7khz); range is 186khz to 217khz, dependent of xtal frequency. frequency offset compensation is only supported for fsk and msk modulation. this register will read 0 when using ook modulation.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 239 of 252 0xdf39: lqi ? demodulator estimate for link quality bit field name reset r/w description 7 crc ok r the last crc comparison matched. cleared when entering/restarting rx mode. 6:0 lqi_est[6:0] r the link quality indi cator estimates how easily a received signal can be demodulated. calcul ated over the 64 symbols following the sync word (first 8 packet bytes for 2-ary modulation, first 16 packet by tes for 4-ary modulation). 0xdf3a: rssi ? received signal strength indication bit field name reset r/w description 7:0 rssi r received signal strength indicator 0xdf3b: marcstate ? main radio control state machine state bit field name reset r/w description 7:5 reserved r0 4:0 marc_state[4:0] r main radio control fsm state value state name state (figure 50, page 209) 0 (0x00) sleep sleep 1 (0x01) idle idle 2 (0x02) xoff xoff 3 (0x03) vcoon_mc mancal 4 (0x04) regon_mc mancal 5 (0x05) mancal mancal 6 (0x06) vcoon fs_wakeup 7 (0x07) regon fs_wakeup 8 (0x08) startcal calibrate 9 (0x09) bwboost settling 10 (0x0a) fs_lock settling 11 (0x0b) ifadcon settling 12 (0x0c) endcal calibrate 13 (0x0d) rx rx 14 (0x0e) rx_end rx 15 (0x0f) rx_rst rx 16 (0x10) txrx_switch txrx_settling 17 (0x11) rx_overflow rx_overflow 18 (0x12) fstxon fstxon 19 (0x13) tx tx 20 (0x14) tx_end tx 21 (0x15) rxtx_switch rxtx_settling 22 (0x16) tx_underflow tx_underflow
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 240 of 252 0xdf3c: pktstatus ? current gdox status and packet status bit field name reset r/w description 7 crc_ok 0 r the last crc comparison matched. cleared when entering/restarting rx mode. 6 cs 0 r carrier sense 5 pqt_reached 0 r preamble quality reached 4 cca 0 r clear channel assessment 3 sfd 0 r start of frame delimiter found 2:0 - 000 r0 not used. 0xdf3d: vco_vc_dac ? current setti ng from pll calibration module bit field name reset r/w description 7:0 vco_vc_dac[7:0] r status register for test only.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 241 of 252 16 voltage regulators the CC2510FX/cc2511fx includes a low drop-out voltage regulator. this is used to provide a 1.8 v power supply to the CC2510FX/cc2511fx digital power supply. the voltage regulator should not be used to provide power to external circuits because of limited power sourcing capability and also due to noise considerations. the voltage regulator input pin avdd_dreg is to be connected to the unregulated 2.0 v to 3.6 v power supply. the output of the digital regulator is connected internally in the CC2510FX/cc2511fx to the digital power supply. the voltage regulator requires an external decoupling capacitor connected to the dcoupl pin as described in section 11 on page 31. 16.1 voltage regulator power-on the voltage regulator is disabled when the CC2510FX/cc2511fx is placed in power modes pm2 or pm3 (see section 13.10). when the voltage regulator is disabled, register and ram contents will be retained while the unregulated 2.0 v - 3.6 v power supply is present. 17 radio test output signals for debug and test purposes, a number of internal status signals in the radio may be output on the port pins p1_7 ? p1_5. this debug option is controlled through the rf registers iocfg2-iocfg0 . table 69 shows the value written to iocfgx.gdox_cfg[5:0] with the corresponding internal signals that will be output in each case.
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 242 of 252 gdo0 _cfg[5:0] gdo1 _cfg[5:0] gdo2 _cfg[5:0] description 0-7 not in use 8 preamble quality reached. asserts when the pqi is above the programmed pqt value. 9 clear channel assessment. high when rssi level is below threshold (dependent on the current cca_mode setting) 10 lock detector output 11 serial clock. synchronous to the data in synchronous serial mode. data is set up on the falling edge and is read on the rising edge of serial_clk. 12 serial synchronous data output. used for synchro nous serial mode. the mcu must read do on the rising edge of serial_clk. data is set up on the falling edge by cc1100. 13 serial transparent data output. used for asynchronous serial mode. 14 carrier sense. high if r ssi level is above threshold. 15 crc ok. the last crc comparison matched. cl eared when entering/restarting rx mode. 16 adc i/q ? serialized 17 decimation filter output i/q + channel filter i/q + cordic + gain 18 demodulator backend key signals (psk) 19 demodulator backend key signals (fsk) 20 data filter output 21 not in use 22 rx_hard_data[1] 23 rx_hard_data[0] 24 fpll 25 clk_pre 26 vco_curr_comp 27 pa_pd 28 lna_pd 29 rx_symbol_tick 30-46 not in use 47 hw to 0 (hw1 achieved with _inv signal) 48-63 not in use table 69: debug output signals
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 243 of 252 18 evaluation software chipcon provides users of CC2510FX/cc2511fx with a software program, smartrf ? studio, which may be used for radio performance and functionality evaluation. smartrf ? studio runs on microsoft windows 95/98 and microsoft windows nt/xp/2000. smartrf ? studio can be downloaded from chipcon?s web page: http://www.ti.com/lpw http://www.chipcon.com
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 244 of 252 19 register overview dph0 (0x83) ? data pointer 0 high byte............................................................................... 38 dpl0 (0x82) ? data pointer 0 low byte ................................................................................ 38 dph1 (0x85) ? data pointer 1 high byte............................................................................... 38 dpl1 (0x84) ? data pointer 1 low byte ................................................................................ 38 dps (0x92) ? data pointer select ........................................................................................... 38 mpage (0x93)? memory page select ................................................................................... 39 psw (0xd0) ? program status word...................................................................................... 43 acc (0xe0) ? accumulator.................................................................................................... 43 b (0xf0) ? b register .......................................................................................................... ... 44 sp (0x81) ? stack pointer ...................................................................................................... .44 ien0 (0xa8) ? interrupt enable 0 register............................................................................. 51 ien1 (0xb8) ? interrupt enable 1 register............................................................................. 52 ien2 (0x9a) ? interrupt enable 2 register............................................................................. 53 tcon (0x88) ? interrupt flag ................................................................................................ 55 s0con (0x98) ? interrupt flag 2............................................................................................ 56 s1con (0x9b) ? interrupt flag 3 ........................................................................................... 56 ircon (0xc0) ? interrupt flag 4 ........................................................................................... 57 ircon2 (0xe8) ? interrupt flag 5 ......................................................................................... 58 ip1 (0xb9) ? interrupt priority 1 ............................................................................................. 5 9 ip0 (0xa9) ? interrupt priority 0............................................................................................. 5 9 memctr (0xc7) ? memory arbiter control ........................................................................ 65 p0 (0x80) ? port 0 ............................................................................................................. ...... 71 p1 (0x90) ? port 1 ............................................................................................................. ...... 71 p2 (0xa0) ? port 2............................................................................................................. ...... 71 percfg (0xf1) ? peripheral control .................................................................................... 71 adccfg (0xf2) ? adc input configuration........................................................................ 72 p0sel (0xf3) ? port 0 function select .................................................................................. 72 p1sel (0xf4) ? port 1 function select .................................................................................. 73 p2sel (0xf5) ? port 2 function select .................................................................................. 74 p0dir (0xfd) ? port 0 direction ........................................................................................... 75 p1dir (0xfe) ? port 1 direction............................................................................................ 76 p2dir (0xff) ? port 2 direction ............................................................................................ 77 p0inp (0x8f) ? port 0 input mode ......................................................................................... 78 p1inp (0xf6) ? port 1 input mode ......................................................................................... 79 p2inp (0xf7) ? port 2 input mode ......................................................................................... 80 p0ifg (0x89) ? port 0 interrupt status flag ........................................................................... 81 p1ifg (0x8a) ? port 1 interrupt status flag .......................................................................... 81 p2ifg (0x8b) ? port 2 interrupt status flag........................................................................... 81 pictl (0x8c) ? port interrupt control................................................................................... 82 p1ien (0x8d) ? port 1 interrupt mask ................................................................................... 83 dmaarm (0xd6) ? dma channel arm .............................................................................. 93 dmareq (0xd7) ? dma channel start request and status................................................ 94 dma0cfgh (0xd5) ? dma channel 0 configuration address high byte ......................... 94 dma0cfgl (0xd4) ? dma channel 0 configuration address low byte .......................... 94 dma1cfgh (0xd3) ? dma channel 1- 4 configuration address high byte...................... 95 dma1cfgl (0xd2) ? dma channel 1- 4 configuration address low byte....................... 95 dmairq (0xd1) ? dma interrupt flag ................................................................................ 95 endian (0x95) ? usb endianess control ( cc2511fx ) ......................................................... 96 t1cnth (0xe3) ? timer 1 counter high ............................................................................ 106 t1cntl (0xe2) ? timer 1 counter low ............................................................................. 106
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 245 of 252 t1ctl (0xe4) ? timer 1 control and status........................................................................ 106 t1cctl0 (0xe5) ? timer 1 channel 0 capture/compare control...................................... 107 t1cc0h (0xdb) ? timer 1 channel 0 capture/compare value high ................................ 107 t1cc0l (0xda) ? timer 1 channel 0 capture/compare value low ................................. 107 t1cctl1 (0xe6) ? timer 1 channel 1 capture/compare control...................................... 108 t1cc1h (0xdd) ? timer 1 channel 1 capture/compare value high ................................ 108 t1cc1l (0xdc) ? timer 1 channel 1 capture/compare value low ................................. 109 t1cctl2 (0xe7) ? timer 1 channel 2 capture/compare control...................................... 109 t1cc2h (0xdf) ? timer 1 channel 2 capture/compare value high................................. 109 t1cc2l (0xde) ? timer 1 channel 2 capture/compare value low.................................. 110 t2ctl (0x9e) ? timer 2 control ......................................................................................... 112 t2ct (0x9c) ? timer 2 count.............................................................................................. 112 t2pr (0x9d) ? timer 2 prescaler......................................................................................... 112 wortime0 (0xa5) ? sleep timer low byte ..................................................................... 114 wortime1 (0xa6) ? sleep timer high byte .................................................................... 114 worevt1 (0xa4) ? sleep timer event0 timeout high .................................................... 114 worevt0 (0xa3) ? sleep timer event0 timeout low..................................................... 114 worctl (0xa2) ? sleep timer control............................................................................. 115 worirq (0xa1) ? sleep timer interrupt control............................................................... 115 t3cnt (0xca) ? timer 3 counter....................................................................................... 120 t3ctl (0xcb) ? timer 3 control ........................................................................................ 120 t3cctl0 (0xcc) ? timer 3 channel 0 capture/compare control..................................... 121 t3cc0 (0xcd) ? timer 3 channel 0 capture/compare value ............................................ 121 t3cctl1 (0xce) ? timer 3 channel 1 capture/compare control ..................................... 122 t3cc1 (0xcf) ? timer 3 channel 1 capture/compare value............................................. 122 t4cnt (0xea) ? timer 4 counter ....................................................................................... 122 t4ctl (0xeb) ? timer 4 control ........................................................................................ 123 t4cctl0 (0xec) ? timer 4 channel 0 capture/compare control ..................................... 124 t4cc0 (0xed) ? timer 4 channel 0 capture/compare value ............................................ 124 t4cctl1 (0xee) ? timer 4 channel 1 capture/compare control ..................................... 125 t4cc1 (0xef) ? timer 4 channel 1 capture/compare value ............................................. 125 timif (0xd8) ? timers 1/3/4 interrupt mask/flag .............................................................. 126 adcl (0xba) ? adc data low.......................................................................................... 130 adch (0xbb) ? adc data high......................................................................................... 130 adccon1 (0xb4) ? adc control 1 ................................................................................... 130 adccon2 (0xb5) ? adc control 2 ................................................................................... 131 adccon3 (0xb6) ? adc control 3 ................................................................................... 132 rndl (0xbc) ? random number generator data low byte ............................................. 134 rndh (0xbd) ? random number generator data high byte ............................................ 134 enccs (0xb3) ? encryption control and status ................................................................. 139 encdi (0xb1) ? encryption input data.............................................................................. 139 encdo (0xb2) ? encryption output data.......................................................................... 139 pcon (0x87) ? power mode control ................................................................................... 142 sleep (0xbe) ? sleep mode control ................................................................................. 142 clkcon (0xc6) ? clock control....................................................................................... 143 wdctl (0xc9) ? watchdog timer control ....................................................................... 146 u0csr (0x86) ? usart 0 control and status .................................................................... 152 u0ucr (0xc4) ? usart 0 uart control ........................................................................ 153 u0gcr (0xc5) ? usart 0 generic control....................................................................... 154 u0dbuf (0xc1) ? usart 0 receive/transmit data buffer.............................................. 154 u0baud (0xc2) ? usart 0 baud rate control................................................................ 154 u1csr (0xf8) ? usart 1 control and status .................................................................... 155 u1ucr (0xfb) ? usart 1 uart control ........................................................................ 156
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 246 of 252 u1gcr (0xfc) ? usart 1 generic control....................................................................... 157 u1dbuf (0xf9) ? usart 1 receive/transmit data buffer .............................................. 157 u1baud (0xfa) ? usart 1 baud rate control ............................................................... 157 fctl (0xae) ? flash control .............................................................................................. 189 fwdata (0xaf) ? flash write data .................................................................................. 189 faddrh (0xad) ? flash address high byte ..................................................................... 189 faddrl (0xac) ? flash address low byte ...................................................................... 189 fwt (0xab) ? flash write timing...................................................................................... 189 rfif (0xe9) ? rf interrupt flags ......................................................................................... 194 rfim (0x91) ? rf interrupt mask........................................................................................ 195
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 247 of 252 20 package description (qlp 36) all dimensions are in millimeters, angles in degrees. note: the CC2510FX/cc2511fx is available in rohs lead-free package only. co mpliant with jedec: mo-220. figure 58: package dimensions drawing quad leadless package (qlp) a a1 a2 d d1 e e1 e b l d2 e2 qlp36 min max 0.80 0.85 0.90 0.005 0.025 0.045 0.60 0.65 0.70 5.90 6.00 6.10 5.65 5.75 5.85 5.90 6.00 6.10 5.65 5.75 5.85 0.50 0.18 0.23 0.30 0.45 0.55 0.65 1.75 4.40 1.75 4.40 the overall package height is 0.85 +/- 0.05 all dimensions in mm table 70: package dimensions
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 248 of 252 20.1 recommended pcb layout for package (qlp 36) figure 59: recommended pcb layout for qlp 36 package note: the figure is an illustration only and not to scale. there are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. see also the CC2510FX em reference design. 20.2 package thermal properties thermal resistance air velocity [m/s] 0 rth,j-a [k/w] 32 table 71: thermal properties of qlp 36 package 20.3 soldering information the recommendations for lead-free reflow in ipc/jedec j-std-020c should be followed. 20.4 tray specification tray specification package tray length tray width tray height units per tray qlp 36 322.6 mm 135.9 mm 7.62 mm 490 table 72: tray specification
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 249 of 252 20.5 carrier tape and reel specification carrier tape and reel is in accordance with eia specification 481. tape and reel specification package carrier tape width component pitch hole pitch reel diameter reel hub diameter units per reel qlp 36 16 mm 12 mm 4 mm 13 inches 7 inches 2500 table 73: carrier tape and reel specification 21 ordering information ordering part number description minimum order quantity cc2510f8rsp 8 kb flash, 1 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2510f8rspr 8 kb flash, 1 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2510f16rsp 16 kb flash, 2 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2510f16rspr 16 kb flash, 2 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2510f32rsp 32 kb flash, 4 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2510f32rspr 32 kb flash, 4 kb ram, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2511f8rsp 8 kb flash, 1 kb ram, full-speed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2511f8rspr 8 kb flash, 1 kb ram, full-speed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2511f16rsp 16 kb flash, 2 kb ram, full-s peed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2511f16rspr 16 kb flash, 2 kb ram, full-s peed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2511f32rsp 32 kb flash, 4 kb ram, full-s peed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, tray with 490 pcs per tray. 490 cc2511f32rspr 32 kb flash, 4 kb ram, full-s peed usb, system-on-chip rf transceiver. qlp36 package, rohs compliant pb-free assembly, t&r with 2500 pcs per reel. 2500 cc2510-cc2511dk CC2510FX and cc2511fx development kit 1 table 74: ordering information
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 250 of 252 22 general information 22.1 document history revision date description/changes 1.0 2005-11-17 first release, preliminary 1.01 2006-05-11 preliminary status updated 1.1 2006-05-30 cc2511fx, cc2510f8 and cc2510f16 added to datasheet. 1.2 2006-07-06 changed recommended pcb layout for package (qlp 36), fig 59 table 75: document history 22.2 product status definitions data sheet identification product status definition advance information planned or under development this data sheet contains the des ign specifications for product development. specif ications may change in any manner without notice. preliminary engineering samples and pre-production prototypes this data sheet contains preliminary data, and supplementary data will be published at a later date. chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible pr oduct. the product at this point is not yet fully qualified. no identification noted full production this data sheet contains the final specifications. chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete not in production this data sheet contains specificat ions on a product that has been discontinued by chipcon. the data sheet is printed for refe rence information only. table 76: product status definitions
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 251 of 252 23 address information texas instruments norway as gaustadallen 21 n-0349 oslo norway tel: +47 22 95 85 44 fax: +47 22 95 85 46 web site: http://www.ti.com/lpw 24 ti worldwide technical support internet ti semiconductor product information center home page: support.ti.com ti semiconductor knowledgebase home page: support.ti.com /sc/knowledgebase product information centers americas phone: +1(972) 644-5580 fax: +1(972) 927-6377 internet/email: support.ti.com/sc/pic/americas.htm europe, middle east and africa phone: belgium (english) +32 (0) 27 45 54 32 finland (english) +358 (0) 9 25173948 france +33 (0) 1 30 70 11 64 germany +49 (0) 8161 80 33 11 israel (english) 180 949 0107 italy 800 79 11 37 netherlands (english) +31 (0) 546 87 95 45 russia +7 (4) 95 98 10 701 spain +34 902 35 40 28 sweden (english) +46 (0) 8587 555 22 united kingdom +44 (0) 1604 66 33 99 fax: +49 (0) 8161 80 2045 internet: support.ti.com/sc/pic/euro.htm japan fax international +81-3-3344-5317 domestic 0120-81-0036 internet/email international support.ti .com/sc/pic/japan.htm domestic www.tij.co.jp/pic
CC2510FX / cc2511fx CC2510FX/cc2511fx preliminary data sheet (rev. 1.2) swrs055a page 252 of 252 asia phone international +886-2-23786800 domestic toll-free number australia 1-800-999-084 china 800-820-8682 hong kong 800-96-5941 india +91-80-51381665 (toll) indonesia 001-803-8861-1006 korea 080-551-2804 malaysia 1-800-80-3973 new zealand 0800-446-934 philippines 1-800-765-7404 singapore 800-886-1028 taiwan 0800-006800 thailand 001-800-886-0010 fax +886-2-2378-6808 email tiasia@ti.com or ti-china@ti.com internet support.ti.com/sc/pic/asia.htm
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